Application Space. Robert F. Kunesh ... test reliability, WLCSP is ideally suited for these mobile ... FM) has required
JANUARY/FEBRUARY 2013 Vol. 40 No. 1
Bumping Wafer Level
Packaging
Flip Chip and Wafer Level Packaging...
Wafer Level Chip Scale Packaging... Embedded Wafer Level Packaging... WWW.IMAPS.ORG
D ev C ice Pa onf Pa ge er ck s en ag 24 c i -2 e ng 9
Electroplating for Bumping...
F E AT U R E A R T I C L E
W
afer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space Robert F. Kunesh, Director, Wafer Level Packaging, Amkor Technology, 1900 South Price Road, Chandler, AZ, USA Phone: 480-786-7532 Contact Email:
[email protected], www.amkor.com Demand for Wafer Level Chip-Scale Packaging (WLCSP) is increasing rapidly, driven largely by adoption in smart phones and tablets. Offering the smallest possible – die sized – footprint as well as robust board level drop test reliability, WLCSP is ideally suited for these mobile applications. Nearly 100% of connectivity devices in handsets now make use of WLCSP, and roughly 92% of all WLCSP packages are assembled into handsets (figure 1). Widespread adoption of WLCSP for highly-integrated wireless connectivity “combo” chips (Bluetooth + WiFi + FM) has required development of processes and materials to extend the qualification envelope for WLCSP to larger die. This packaging technology is now in use for devices nearing 7mm/side, with I/O counts greater than 200. While connectivity devices are driving WLCSP on 300mm wafers, typically at the 65nm technology node, analog and mixed signal applications continue to represent a major portion of WLCSP demand. Analog and mixed signal die are typically smaller, built with larger technology nodes (180 – 130nm) on 200mm wafers. WLCSP development has evolved along two paths, with focus on simplified process flows to reduce capital intensity and cycle time, and on new materials to maximize board level reliability for large die.
Three Process Flows Enable Many Applications
Amkor’s WLCSP offerings include 2, 3 and 4-mask process flows, a choice of two polymer repassivation materials, and two under bump metal (UBM) options (figure 2). The simplest, CSPnl Bump on Repassivation (BoR) structure requires die that are designed for WLCSP. Aluminum pads must be located where solder balls are desired. Redistributed structures, which use plated copper to connect aluminum pads to solder balls in a different location, are more widely applicable and offer a board level reliability benefit. The 4-mask, CSPnl structure has been
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in production since 2006. The 3-mask, CSPn3 structure was first qualified in 2009, and has since gained wide acceptance. One billion CSPn3 devices are expected to ship in 2013. This article will briefly examine three trends impacting WLCSP demand, each requiring a different approach to identifying the optimum structure for cost and performance.
Redistribution
The simplest process flow can be expected to have lowest cost and shortest cycle time. As noted above, a Bump on Repassivation structure requires two masking levels, while most flows with a redistribution layer involve three or four. What drives choice of a more complex process? One answer is the ability to re-use an existing die by adding redistribution. The same die, with peripheral bond pads, can be put in a package (MLF/QFN, for example) or converted to WLCSP, with balls in an array, by adding redistribution. Another driver for the addition of redistribution is board level reliability. Amkor recently conducted board level drop testing of two die with identical package outline drawing (POD). Both were 3.5mm die, with a de-populated 8x9 ball array. One of these was packaged using the 2-mask BoR structure, the other with the 4-mask CSPnl structure. Both structures exceeded typical requirements for customer qualification (figure 3). The simpler, BoR structure has cost and cycle time advantages. The RDL structure demonstrated superior drop test performance, and would be suitable for more demanding applications. As die size increases, redistribution becomes critical for meeting reliability targets. This is particularly true for die with low-K dielectrics. The addition of redistribution places a buffer between the solder ball and fragile low-K structures.
JANUARY/FEBRUARY 2013
Figure 1: Link between handsets and WLCSP demand (courtesy Yole Developpement).
Advancing Technology Nodes
WLCSP has been utilized extensively at the 65nm technology node, and is gaining some traction at 45nm. The continual march to smaller [front end fab] feature size presents a challenge to the continued 1:1 ratio of die size to package size that distinguishes WLCSP. A majority of current WLCSP designs employ 400um (0.4mm) pitch between solder balls to comply with existing board technology. At the 28nm node, I/O density can easily exceed what can be packed onto the available silicon at 400um pitch. By unit volume, the 180nm and 130nm silicon nodes still account for the largest share of WLCSP production. Demand for analog and mixed signal devices at these nodes will continue for some time. The I/O density challenge of newer technology nodes will be met by WLCSP with finer solder ball pitch at some point in the future. Existing wafer level packaging processes can accommodate 300um ball pitch, but this may drive finer pitch or additional layers at the board level – and associated cost. It appears 350um pitch will be adopted first, to minimize impact at the board level.
Power Consumption
Figure 2: WLCSP structures.
WLCSP has become the predominant packaging solution for power management and power amplifier devices used in handsets. Thick RDL copper is often requested for these devices, to accommodate high current. In some cases die size has grown significantly, to maintain 400um pitch and increase the number of balls to minimize current density. A majority of these devices are built on the 180nm technology node, and they represent an uncommon combination of large die size and 200mm wafers. Thicker copper drives thicker polymer repassivation, and this combination has often improved board level reliability – thus enabling the larger die. Development is currently focused on increased amps/ball, to reduce the number of bumps and thereby reduce die size. continued on page 16 15
A DVA N C I N G
MICROELECTRONICS
continued from page 15
Summary
All the available WLCSP solutions share the smallest possible package footprint, making them attractive for use in mobile devices. Within those mobile devices there are a variety of chips, each of which brings a unique set of requirements. Selection of the appropriate WLCSP structure and materials is critical to achieving the best combination of cost and benefit. Bob Kunesh is Director, Wafer Level Packaging, at Amkor Technology. He has worked in the semiconductor industry for over 30 years, including more than ten in wafer level packaging and test. Prior to joining Amkor, Bob held positions in process and equipment engineering and operations management at Texas Instruments and IBM.
Figure 3: Drop test performance of competing structures.
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