pvt build - SwiftLife Inc.

8

6

7

REV

ZONE

ECN

ENG APPD

DESCRIPTION OF CHANGE DATE

M97 MLB SCHEMATIC

A

625211

PRODUCTION RELEASED

DATE

08/29/08 ?

REFERENCED FROM T18 08/27/2008

D (.csa)

Date

Page TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM































B

1 CK APPD

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

C

2

3

4

5




1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Contents

Sync

1

Table of Contents

(.csa)

System Block Diagram

08/22/2007

TABLE_TABLEOFCONTENTS_HEAD

12/12/2007


03/13/2008


T18_MLB

3

Power Block Diagram

DRAGON TABLE_TABLEOFCONTENTS_ITEM

4

BOM Configuration

M97_MLB TABLE_TABLEOFCONTENTS_ITEM

5

Revision History

M97_MLB

6

04/04/2008

JTAG Scan Chain


BEN TABLE_TABLEOFCONTENTS_ITEM

7

FUNC TEST

M97_MLB

Power Aliases

BEN

SIGNAL ALIAS

M97_MLB

8

04/21/2008



9 10

CPU FSB

12/12/2007


12/12/2007


03/31/2008


12/12/2007


T18_MLB

11

CPU Power & Ground

T18_MLB

12

CPU Decoupling

RAYMOND

eXtended Debug Port (XDP)

T18_MLB

13 14

MCP CPU Interface

04/04/2008


04/04/2008


04/04/2008


T18_MLB

15

MCP Memory Interface

T18_MLB

MCP Memory Misc

T18_MLB

MCP PCIe Interfaces

T18_MLB

16 17 18

MCP Ethernet & Graphics

04/04/2008


04/04/2008


04/04/2008


04/04/2008


06/26/2008


04/04/2008


03/08/2008


T18_MLB

19

MCP PCI & LPC

T18_MLB

20

MCP SATA & USB

T18_MLB

21

MCP HDA & MISC

T18_MLB

22

MCP Power & Ground

T18_MLB

MCP79 A01 Silicon Support

T18_MLB

24 25

MCP Standard Decoupling

04/04/2008


12/12/2007


04/05/2008


03/31/2008


06/30/2008


05/09/2008


04/04/2008


T18_MLB

26

MCP Graphics Support

T18_MLB

28

SB Misc

RAYMOND

29

FSB/DDR3 Vref Margining

BEN

31

DDR3 SO-DIMM Connector A

BEN

32

DDR3 SO-DIMM Connector B

BEN

DDR3 Support

T18_MLB

33 34

Right Clutch Connector VENICE CONNECTOR


03/13/2008


05/23/2008


07/01/2008


04/04/2008


YITE

37

Ethernet PHY (RTL8211CL)

SUMA

38

Ethernet & AirPort Support

SUMA

ETHERNET CONNECTOR

SUMA

39

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Contents 45

SATA Connectors External USB Connectors Front Flex Support SMC SMC Support M97 SMBUS CONNECTIONS


P

05/28/2008


05/09/2008


04/21/2008


02/04/2008


YUNWU

54

04/07/2008

Current Sensing

100

Sync 01/04/2008

CPU/FSB Constraints

T18_MLB

Memory Constraints

T18_MLB

MCP Constraints 1

T18_MLB

MCP Constraints 2

T18_MLB

Ethernet Constraints

T18_MLB

101 102 103 104 106

01/04/2008 01/04/2008 12/14/2007 03/19/2008

T18_MLB

M97 SPECIAL CONSTRAINTS

M97_MLB

M97 RULE DEFINITIONS

M97_MLB

109


03/20/2008

Thermal Sensors

YUNWU

56

01/18/2008

Fan

CHANGZHANG

57

04/22/2008

WELLSPRING 1

YUAN.MA

58

05/09/2008

WELLSPRING 2

YUAN.MA

59

06/26/2008

SMS

YUNWU

61

05/02/2008

SPI ROM

01/04/2008

SMC Constraints

107

YUNWU

55

C

CHANGZHANG

62

07/01/2008

AUDIO: CODEC

AUDIO

63

07/03/2008

AUDI0: MIKEY

AUDIO

66

07/01/2008

AUDI0: SPEAKER AMP

AUDIO

67

07/01/2008

AUDIO: JACK 68

AUDIO

m il

AUDIO: JACK TRANSLATORS 69

DC-In & Battery Connectors 70

PBUS Supply/Battery Charger 72

5V/3.3V SUPPLY 73

1.5V/0.75V DDR3 SUPPLY 74

IMVP6 CPU VCore Regulator 75

MCP VCORE REGULATOR 76

07/01/2008

AUDIO

03/13/2008

JACK

01/31/2008

RAYMOND

02/08/2008

RAYMOND

01/31/2008

RAYMOND

01/31/2008

RAYMOND

01/31/2008

RAYMOND

02/08/2008

CPU VTT(1.05V) SUPPLY

RAYMOND

MISC POWER SUPPLIES

RAYMOND

77



BEN

VOLTAGE SENSING

98

06/26/2008

CHANGZHANG

53

97


71 72 73 74 75 76 77 78

Date

Contents

a n i

LPC+SPI Debug Connector 52

94

05/28/2008

YUAN.MA

51

93


T18_MLB

50

90

TABLE_TABLEOFCONTENTS_HEAD

YUAN.MA

49

79

04/14/2008 01/18/2008 YUAN.MA

48

78

Page

CHANGZHANG

46

y r

(.csa)

Sync

e r

04/22/2008 YITE

35

Date

Page

T17_MLB

2

D

01/23/2008 04/22/2008

POWER SEQUENCING

YUAN.MA

POWER FETS

YUAN.MA

LVDS CONNECTOR

NMARTIN

DISPLAYPORT SUPPORT

AMASON

DisplayPort Connector

AMASON

LCD BACKLIGHT DRIVER

YITE

LCD Backlight Support

YITE

04/04/2008 04/04/2008 04/18/2008

B

06/30/2008 08/12/2008 06/30/2008

PVT BUILD A

DIMENSIONS ARE IN MILLIMETERS

X.XX DRAFTER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

051-7537

1

SCHEM,MLB,M97

SCH

CRITICAL

820-2327

1

PCBF,MLB,M97

PCB

CRITICAL

A

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

X.XXX

Schematic / PCB #’s PART NUMBER

APPLE INC.

METRIC

XX

TITLE

DO NOT SCALE DRAWING

BOM OPTION

SCHEM,MLB,M97 NONE SIZE

THIRD ANGLE PROJECTION

8

7

6

5

4

3

MATERIAL/FINISH NOTED AS APPLICABLE

D

DRAWING NUMBER

REV.

051-7537

A SHT

2

1

1

OF

109

8

6

7

2

3

4

5

1

U1000

U1300

INTEL CPU XDP CONN

2.X OR 3.X GHZ

PG 12

PENRYN PG 9

FSB

D

D

J6950

64-Bit 800/1067/1333 MHz

y r

DC/BATT

POWER SUPPLY

PG 13 PG 60

J2900

2 UDIMMs MAIN FSB INTERFACE

GPIOs

DDR2-800MHZ DDR3-1067/1333MHZ

MEMORY

DIMM

PG 14

U4900 PG 25,26

TEMP SENSOR PG 41

Misc

a n i

CLK PG 24 U6100

SYNTH

POWER SENSE PG 45

SPI Boot ROM

J4510

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

SPI

SATA

PG 52

Conn

1.05V/3GHZ.

PG 48,49

PG 20

PG 38

HD

NVIDIA

J4520

J4900

B,0

SATA Conn

C

LPC

ODD

Prt

LPC Conn

Port80,serial

C

PG 43

PG 18

J9000

PWR

LVDS CONN

CTRL

LVDS OUT

PG 71

m il

RGB OUT

J4720

DP OUT

HDMI OUT

PG 16

PCI-E

PCI

(UP TO FOUR PORTS)

PG 17

PG 18

P

9 8 7 6

PG 39

2 1 0

UP TO 20 LANES3

e r RGMII

EXTERNAL USB

Connectors

PG 40

PG 40

5

PG 17

PG 40

J3900,4635,4655

CAMERA

4

USB

TMDS OUT

J4710

IR

3

DVI OUT PG 71

J4710

TRACKPAD/ KEYBOARD

PG 40

PG 19

DISPLAY PORT CONN

J4700

Bluetooth

(UP TO 12 DEVICES)

J9400

A

Ser

PG 41

U1400

B

Fan

SMC

PG 19

PG 38

ADC

BSB

J5100

MCP79

SATA

1.05V/3GHZ.

B

SMB

SMB

PG 20

CONN

HDA

PG 44

DIMM’s

PG 20

U6200

Audio Codec PG 53

U6301

U6400

U6500

System Block Diagram

U6600,6605,6610,6620

U3700

GB

Line In

Line Out

Speaker

E-NET

Amp

Amp

Amp

Amps

PG 54

PG 55

PG 56

PG 57

HEADPHONE

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2007


88E1116 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PG 31

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE J3400

II NOT TO REPRODUCE OR COPY IT

U3900

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Mini PCI-E

J6800,6801,6802,6803

E-NET

AirPort

Conn

PG 28

Audio

SIZE

Conns

D

PG 33 PG 59

APPLE INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 2

1

109

A

8

6

7

2

3

4

5

1

M97 POWER SYSTEM ARCHITECTURE D6905

02 PPVIN_G3H_P3V42G3H

D6905

V

7A FUSE PPVBAT_G3H_CHGR_REG

D

ENABLE

VIN

SMC_BATT_ISENSE

ISL6258A U7000

CPU VCORE

A SMC_CPU_ISENSE PPVCORE_CPU_S0_REG (44A MAX CURRENT)

VOUT

VIN

J6950

ISL9504B IMVP_VR_ON

Q7050

VR_ON

28

25

PPVBAT_G3H_CHGR_OUT

SMC_CPU_VSENSE

V

U5480

01

VR_PWRGOOD_DELAY

PGOOD

U7400

06 P1V05S0_EN

1.05V SO

PP1V05_S0_FET

FETS

CHGR_BGATE

PPBUS_G3H

(Q7951 TO Q7953)

1.05V (S5)

26

22

4.6V AUDIO MAX8902A

VIN

U6201

MCP79

11

11-1

P3V3S3_EN

RC DELAY

PM_SLP_S4_L

11-3

RC DELAY

U1400

P60

P5VRTS0_EN_L

04

U4900

DDRREG_EN

SMC_PM_G2_EN

05

Q7800

(S5)

P3V3S5_EN_L

02

11-2

e r

VIN

BKLT_EN

B

GOSHAWK6P U9701 ENA

VOUT

15 PM_SLP_S3_L

1.2V YUKON VIN U3850

Q3801 PM_ENET_EN_L

PPVOUT_S0_LCDBKLT

ENETADD_EN

16

Q3802 WOL_EN SMC_ADAPTER_EN

04-1

P 02

VIN

=DDRREG_EN

=DDTVTT_EN

PM_SLP_S3_L

A

RC DELAY

RC DELAY

RC DELAY

RC DELAY

P1V8S0_EN

16-3

MCPDDR_EN 16-2

CPUVTTS0_EN

MCPCORES0_EN

8

16-3

16-4

16-2

P1V05S0_EN (S0) P3V3S0_EN (S0) PBUSVSENS_EN (S0) P5VRTS0_EN_L (S0)

7

S5 S3

PP5VRT_S0_REG

VOUT1

(4A MAX CURRENT)

VOUT2

3.3V

EN2

(4A MAX CURRENT)

Q7910

PGOOD1,2

VOUT2

RESET*

U1000

07

PP3V3_S3_FET

13

RSMRST_OUT(P15)

PP3V3_S0_FET

PWRGD(P12)

18 09

RSMRST_PWRGD SMC_ONOFF_L

05

MCPCORESO_PGOOD CPUVTTS0_PGOOD

SLP_S5_L

99ms DLY

IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) P17(BTN_OUT)

IMVP_VR_ON

B

25

PM_PWRBTN_L SMC_RESET_L

SLP_S4_L(P94)

SLP_S3_L

SLP_S3_L(P93)

U4900

S0PGOOD_PWROK

21

10

SLP_S5_L(P95)

SLP_S4_L

P5V_LT_S3_PGOOD PP1V5_S0

PM_RSMRST_L

RST*

R5491 PP1V5_S0_FET

1.8V LDO

14

TPS79918DRV U7760

TPS51116 U7300

PP1V8_S0_REG

19-1

RST*

PP0V75_S0_REG (1A MAX CURRENT)

PP3V3_S0

V1

PP1V5_S0

V2

PP1V05_S0

20 EN2

SMC

24 ALL_SYS_PWRGD

P3V3S0_EN Q3810 P3V3_ENET_FET

PP1V5_S3_REG (12A MAX CURRENT)

VOUT2

32

17

P5V3V3_PGOOD

VOUT1

MCP_CORE

C

CPU PWRGOOD

PP3V3_S5

P3V3ENET_EN_L

1.5V

MCPCORES0_EN

U1400

PP4V6_AUDIO_ANALOG

PP5VRT_S0

Q7930

(Q7901 & Q7971)

16-2

30 CPU_RESET#

P3V3S3_EN

(0.8A MAX CURRENT)

S3 TO S0 FETS

0.75V VOUT2

U2850

P5V3V3_PGOOD

PP1V2_ENET_REG

RUN2

CPU_PWRGD

CPUPWRGD(GPIO49)

VREG3

(0.8A MAX CURRENT)

LTC34074

P1V2ENET_EN

5V

(RT)

29

(1.9V) PPVOUT_ENET_AVDD_REG

VOUT1

RUN1

VIN

EN1

TPS51125 U7200

SMC_PM_G2_EN

P5VLTS3_EN

RC DELAY

08

PP3V3_S5_REG

PCI_RESET0#

15-1

VOUT

RSMRST*

MCP_PS_PWRGD PS_PWRGD

PP1V05_S5_REG

m il

P16

15

U7750

02

SMC SLP_S3#

TPS62510

06 P1V05_S5_EN

31 LPC_RESET_L

PLTRST*

VOUT

EN

06-1

PWRBTN*

FSB_CPURST_L

a n i

CPUVTTS0_PGOOD

02

BATT_POS_F

MCP79

PGOOD

A

SMC_DCIN_ISENSE

(9 TO 12.6V)

PPCPUVTT_S0

TPS51117 U7600

U5403

VOUT

PBUS SUPPLY/ BATTERY CHARGER

C

VOUT

CPUVTT

ENABLES

A

3S2P

y r

R5492

PPCPUVTT_S0_REG_R (8A MAX CURRENT)

(1.05V)

U7970

6A FUSE

D

23

VIN EN_PSV

04

U5000

02

CPUVTTS0_EN (S0)

CHGR_EN (S5)

SMC PWRGD RN5VD30A-F

Q5315

PPBUS_G3H

01

AC DCIN(16.5V) ADAPTER IN

PP3V42_G3H_REG 03

3.425V G3HOT LT3470 VOUT U6990

PBUS_VSENSE

R5490

PPVCORE_S0_MCP_REG_R

V3

Power Block Diagram SYNC_MASTER=DRAGON

LTC2909 U7870


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PPVCORE_S0_MCP

(25A MAX CURRENT)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

P5VLTS3_EN

16-2

5V (LT)

11-2

EN1

PP5VLT_S3_REG

12


PP5VLT_S3

VOUT1

SIZE

(7A MAX CURRENT)

02

6

DRAWING NUMBER

D

VIN

16-1

APPLE INC.

ISL6236

U7500

SCALE

SHT NONE

5

4

3

2

REV.

051-7537

A

OF 3

1

109

A

8

6

7

BOM Variants

2

3

4

5

1

Bar Code Labels / EEE #’s TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS

630-9554

PCBA,MLB,BETTER,M97

M97_COMMON,CPU_2_0GHZ,EEE_2KA

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

TABLE_BOMGROUP_ITEM

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:2K9]

CRITICAL

EEE_2K9

826-4393

1


[EEE:2KA]

CRITICAL

EEE_2KA

826-4393

1


[EEE:1DJ]

CRITICAL

EEE_1DJ

TABLE_BOMGROUP_ITEM

630-9314

PCBA,MLB,BEST,M97

M97_COMMON,CPU_2_4GHZ,EEE_1DJ

BOM Groups

D

D

TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

M97_COMMON

COMMON,ALTERNATE,M97_MCP,M97_MISC,M97_DEBUG_PVT,M97_PROGPARTS

M97_MCP

MCP_B02,MCP_PROD,MEMRESET_HW,MEMRESET_MCP,BOOT_MODE_USER,MCPSEQ_SMC,MCP_CS1_NO

M97_MISC

ONEWIRE_PU,BKLT_PLL_NOT,DP_ESD,ENG_BMON,MIKEY

M97_PROGPARTS

BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG

M97_DEBUG_ENG

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG

M97_DEBUG_PVT

SMC_DEBUG_YES,XDP,LPCPLUS,NO_VREFMRGN

M97_DEBUG_PROD

SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

TABLE_BOMGROUP_ITEM

y r

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

a n i

Module Parts PART NUMBER

C

DESCRIPTION

REFERENCE DES

337S3622

QTY 1

PDC,QJGL,QS,2.0,25W,1066,M0,3M,BGA

U1000

CRITICAL CRITICAL

BOM OPTION CPU_2_0GHZ_QS

337S3624

1

PDC,QDYD,QS,2.26,25W,1066,M0,3M,BGA

U1000

CRITICAL

CPU_2_26GHZ_QS

337S3625

1

PDC,QDYJ,QS,2.4,25W,1066,M0,3M,BGA

U1000

CRITICAL

CPU_2_4GHZ_QS

337S3646

1

PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA

U1000

CRITICAL

CPU_2_0GHZ

337S3653

1

PDC,SL3BU,PRQ,2.26,25W,1066,C0,3M,BGA

U1000

CRITICAL

CPU_2_26GHZ

337S3639

1

PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA

U1000

CRITICAL

CPU_2_4GHZ

338S0540

1

IC,GMCP,MCP79,35X35MM,BGA1437,A01

U1400

CRITICAL

MCP_A01

338S0591

1

IC,GMCP,MCP79,35X35MM,BGA1437,A01P

U1400

CRITICAL

MCP_A01P

338S0603

1

IC,GMCP,MCP79,35X35MM,BGA1437,A01Q

U1400

CRITICAL

MCP_A01Q

338S0600

1

IC,GMCP,MCP79,35X35MM,BGA1437,B01

U1400

CRITICAL

MCP_B01

338S0635

1

IC,GMCP,MCP79,35X35MM,BGA1437,B02

U1400

CRITICAL

MCP_B02

338S0570

1

IC,RTL8211CL,GIGE TRANSCEIVER,48P,TQFP

U3700

CRITICAL

m il

Programmable Parts 338S0563

1

IC,SMC,HS8/2117,9X9MM,TLP,HF

U4900

CRITICAL

341S2287

1

IC,SMC,M97

U4900

CRITICAL

SMC_BLANK SMC_PROG

335S0610

1

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

U6100

CRITICAL

BOOTROM_BLANK

341S2285

1

IC,PRGRM,EFI BOOTROM,UNLOCK,M97

U6100

CRITICAL

BOOTROM_PROG

338S0375

1

IC,CY7C63833,ENCORE II,USB CONTROLLER

U4800

CRITICAL

IR_BLANK

341S2093

1

IC,IR CONTROLLER,M97

U4800

CRITICAL

IR_PROG

337S2983

1

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

U5701

CRITICAL

WELLSPRING_BLANK

341S2348

1

IC,WELLSPRING CONTROLLER,M97

U5701

CRITICAL

WELLSPRING_PROG

e r

B Alternate Parts TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

152S0778

152S0693

ALL

CYNTEC AS ALTERNATE

152S0796

152S0685

ALL

CYNTEC AS ALTERNATE

152S0694

152S0138

ALL

MAGLAYERS AS ALTERNATE

157S0058

157S0055

ALL

DELTA AS ALTERNATE

104S0018

104S0023

ALL

DALE/VISHAY AS ALTERNATE

128S0093

128S0218

ALL

KEMET AS ALTERNATE

152S0874

152S0516

ALL


152S0847

152S0586

ALL


514-0612

514-0607

ALL

FOXLINK AS ALTERNATE

514-0613

514-0608

ALL

FOXLINK AS ALTERNATE

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

A

P

C

M97 BOARD STACK-UP

Top 2 3 4 5 6 7 8 9 10 11 BOTTOM

SIGNAL GROUND SIGNAL(High SIGNAL(High GROUND POWER POWER GROUND SIGNAL(High SIGNAL(High GROUND SIGNAL

Speed) Speed)

B

Speed) Speed)

BOM Configuration SYNC_MASTER=M97_MLB

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

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051-7537

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Revision History

D

D

y r

a n i

C

C

m il

e r

B

P

A

B

A SYNC_MASTER=M97_MLB

A


DRAWING NUMBER

D APPLE INC.

NOTE: All page numbers are .csa, not PDF.

8

7

6

SCALE

SHT NONE

See page 1 for .csa -> PDF mapping.

5

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051-7537

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OF 5

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D

D 1.05V TO 3.3V LEVEL TRANSLATOR (M97: ON ICT FIXTURE)

y r

=PP3V3_S0_XDP 13D6 8C5

To XDP connector and/or level translator

=PP1V05_S0_CPU 12B6 11C6 10D5 8D7 13D6

U1000 CPU

From XDP connector JTAG_ALLDEV 1

C0601

JTAG_ALLDEV 1

0.1UF

C0602 0.1UF

20% 2 10V CERM 402

20% 2 10V CERM 402

71A3 13B6 10C6 10A6 6C7

IN

71A3 13B3 10C6 10B6

IN

71A3 13B3 10C6 10B6 6C7

IN

71A3 13B3 10C6 10A6 6C7

IN

XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L

XDP

a n i R0603

71A3 10C6 10B6

XDP_TDO

0

XDP_TDO_CONN

5% 1/16W MF-LF 402

JTAG_ALLDEV

R06011 1

11

10K 5% 1/16W MF-LF 402 2

From XDP connector or via level translator

VCCA VCCB

U0600

C

U1400 MCP

NLSV4T244

71A3 13B6 10C6 10A6 6C6

XDP_TCK

NOSTUFF

R06021 0 5% 1/16W MF-LF 402 2

71A3 13B3 10C6 10B6 6C6 71A3 13B3 10C6 10A6 6C6

XDP_TMS XDP_TRST_L

JTAG_LVL_TRANS_EN_L

2 3 4 5 12

UQFN A1 A2 A3 JTAG_ALLDEV A4

B1 B2 B3 B4

JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L

10 9 8 7

13B6 21B7

13B3

C

XDP

13C3 21B7 23C5

R0604

13C3 21B7 23C5 13C3 21B7

OUT

XDP connector

21B7

JTAG_MCP_TDO

0

JTAG_MCP_TDO_CONN

5% 1/16W MF-LF 402

OE* GND

OUT

13C3

XDP connector

6

m il

e r

B

P

A

B

JTAG Scan Chain SYNC_MASTER=BEN



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

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REV.

051-7537

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109

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Functional Test Points RIGHT CLUTCH CONN PP5V_S3_BTCAMERA_F TRUE PCIE_MINI_D2R_P TRUE PCIE_MINI_D2R_N TRUE PCIE_MINI_R2D_P TRUE PCIE_MINI_R2D_N TRUE PCIE_CLK100M_MINI_CONN_P TRUE PCIE_CLK100M_MINI_CONN_N TRUE USB_CAMERA_CONN_P TRUE USB_CAMERA_CONN_N TRUE PP5V_WLAN TRUE PCIE_WAKE_L TRUE SMBUS_SMC_A_S3_SCL TRUE SMBUS_SMC_A_S3_SDA TRUE CONN_USB2_BT_P TRUE CONN_USB2_BT_N TRUE MINI_CLKREQ_Q_L TRUE MINI_RESET_CONN_L TRUE

Fan Connectors

D

I12 I15 I16

TRUE TRUE TRUE

PP5VRT_S0 FAN_RT_PWM FAN_RT_TACH

(NEED 3 TP) 7D3 8D5

I303

46B4

I301

(NEED TO ADD 3 GND TP)

I238 I237 I239

31B7

I227

I298 I293 54B1 54D2 54B1 54D2

I226

54D2 55A6

I228 I230 I229 I231

I232 I233

I259 I258

C

I260 I245 I262 I261 I256 I257 I255 I252 I253 I254 I250 I251 I313 I246 I247 I248 I249

53C3 54C2

I290

53C3 54C2

I271

53B2 54C2

I289

I269 I267 I265 I266

B I312 I304

I321 I320

THERMAL FUNC_TEST MCPTHMSNS_D2_P TRUE MCPTHMSNS_D2_N TRUE LVDS FUNC_TEST PP3V3_LCDVDD_SW_F TRUE PP3V3_S0_LCD_F TRUE PPVOUT_S0_LCDBKLT TRUE LVDS_IG_DDC_CLK TRUE LVDS_IG_DDC_DATA TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_DATA_N TRUE LVDS_IG_A_DATA_P TRUE LVDS_IG_A_CLK_F_N TRUE LVDS_IG_A_CLK_F_P TRUE LED_RETURN_1 TRUE LED_RETURN_2 TRUE LED_RETURN_3 TRUE LED_RETURN_4 TRUE LED_RETURN_5 TRUE LED_RETURN_6 TRUE

31B7 74B3

45B5 77D3

I314

45B5 77D3

I315 I318 I317

7C3 66C2

I316

I325

I310 I311 I309 I308 I307

I393

(NEED 4 TP)

I392

7C3 36A7

I391

36A7 73A3

I390

36A7 73A3

I389

36A7 73A3

I388

36A7 73A3

I387

7B7 36B5 73A3

I386 I385

7C3 66B2 69B3 69C1

I384

18A3 66C5 18A3 66B5 18B3 66C2 73B3

I375

18B3 66C2 73B3

I374

18B3 66C2 73B3

I373

18B3 66C2 73B3

I372

18B3 66C2 73B3

I370

18B3 66C2 73B3

I371

66B2 73B3

I369

66B2 73B3

I368

66B3 69C1

I361

66B3 69B1

I366

66B3 69B1

I367

66B3 69B1

I365

66B3 69B1

I363

66B3 69B1

I364

47C8 48C3 48C3 48C5 47D8 48C3 47C8 48C3 47B6 48C3 47C8 48C1 47C8 48C1 47C8 48C1 47C8 48C1

e r

I377 36B5 73A3

I378 36B5 73A3 36B5 73A3 7C5 36B5 73A3

KEYBOARD CONN

I354 I355 I344 I345

P I348

(NEED 3 TP) (NEED 3 TP) 7A7 42C5 76D3

I350

56A8

I352

56A8

I351 I353

7A7 42C5 76D3

I327

39C5 40B2 56A8

BATT SIGNAL CONN (NEED 3 TP) PP3V42_G3H TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_DB_L TRUE

I342 I341

7B5 7C3 8D1

I339

7A7 42C5 76D3 7A7 42C5 76D3 56A5

I340 I338 I336


I337

FRONT FLEX CONN PP3V42_G3H_LIDSWITCH_R TRUE PP5V_S3_IR_R TRUE IR_RX_OUT TRUE SMC_LID_R TRUE SYS_LED_ANODE_R TRUE 38B6

I335

38B6

8D7 8C7

y r 8C7 8C7 8B7 8B7

7D7 8D5 8C5 8D3

7B5 8D3 8C3 8B3 8B3

7A7 7B5 8D1 8C1 8B1 8B1

21C8 22A5 26D4 7D5 31C5 7B7 36D3 7C5 36A7

39D4 40B6

7C5 48C1 48D3 7C5 48B4 48C3 7C7 66C2

7C7 66B2 69B3 69C1

C

69A8 69B6 69C4 69C8 51A3 51D3 52D6

39D5 64D8 21C3 39C5 40A2 64C8

21C3 34B7 39C5 41A5 64D5 68D8

47C8 48C1

I358

BATT POWER CONN PPVBAT_G3H_CONN_F TRUE GND_BATT_CONN TRUE SMBUS_SMC_BSA_SCL TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BS_ALRT_L TRUE

D

8D7

m il 47C8 48C3

36B7 39B8

56D7

PPVCORE_S0_CPU PPCPUVTT_S0 PPVCORE_S0_MCP PP0V75_S0 PP1V05_S0 PP1V5_S0 PP1V8_S0 PP5VRT_S0 PP3V3_S0 PP1V5_S3 PP3V3_S3 PP5VLT_S3 PP1V1R1V05_S5 PP3V3_S5 PP3V42_G3H PPBUS_G3H PP3V3_ENET_PHY PP1V2R1V05_ENET PP3V3_G3_RTC PP5V_WLAN PP5V_SW_ODD PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC PP18V5_S3 PP3V3_S3_LDO PP3V3_LCDVDD_SW_F PPVOUT_S0_LCDBKLT BKL_VREF_4V9 PP4V6_AUDIO_ANALOG SMC_PM_G2_EN PM_SLP_S4_L PM_SLP_S3_L


47C8 48C3

I357

(NEED 3 TP) 56D6

I380

47C8 48C3

36D3


I381

47C8 48C3


DC POWER CONN PP18V5_DCIN_FUSE TRUE ADAPTER_SENSE TRUE

I382

7C3 48C1 48D3

I359

4 TP) 7C3

I383

48B4 48C3 48C4 48C7

I362

SATA ODD CONN (NEED PP5V_SW_ODD TRUE SMC_ODD_DETECT TRUE SATA_ODD_D2R_C_P TRUE SATA_ODD_D2R_C_N TRUE SATA_ODD_R2D_P TRUE SATA_ODD_R2D_N TRUE

IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE

7C3 48B4 48C3

I333

A

I276


66C3

I343

I324

I275

31A7

SATA HDD CONN PP5V_S0_HDD_FLT TRUE SATA_HDD_R2D_P TRUE SATA_HDD_R2D_N TRUE SATA_HDD_D2R_C_P TRUE SATA_HDD_D2R_C_N TRUE SATA_ODD_R2D_N TRUE

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

a n i I274

31C7

I319

I329

I323

I273

I272

I328

I326

I379


I349

I322

I270

31B7 74B3

I347

I306

I278

7B5 42D2 76D3

I346

I305

I279

7B5 42D2 76D3

I360

I268

I283

53B2 54C2


I264

I376

17B6 23C5 31C7

I296

I295

I282

7C3 31C5

I292

53B2 54C2

I281 31C8 73D3

31B7 74C3

I294

I291

I280 31C8 73D3

31B7 74C3

I297

53A2 54C2

I284

31C7 73D3

I299

FUNC_TEST SPKRAMP_L_N_OUT SPKRAMP_L_P_OUT SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT

I285

31C7 73D3

I288

SPEAKER TRUE TRUE TRUE TRUE TRUE TRUE

I286

17B6 31C7 73D3

I300

MIC FUNC_TEST MIC_HI_CONN TRUE MIC_LO_CONN TRUE MIC_SHLD_CONN TRUE

I287

17B6 31C7 73D3

I302

46C4

DEBUG VOLTAGE

I334 I332 I330

38A4 38C4

I331

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

7C5 42D2 76D3

7D5 42D2 76D3

47C8 48C1 47D8 48C1

PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

B

7D3 8D3

7A7 7C3 8D1 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C6 47D2 47C2 47C6 47C2 47C6 47C2 47C6 47C2 47C6 47C2 47C2 47C2 47C6 47C2 47D7 47C2 47D7 47C2 47D7

FUNC TEST

47C2 47D7 47C2 47D7

SYNC_MASTER=M97_MLB

47C2 47D7

47B3 47B5 47C2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

47B3 47B5 47C2

47B3 47B5 47C2


38B6

A


47C2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

38B6




I356

KBD BACKLIGHT CONN KBDLED_ANODE TRUE

SIZE

DRAWING NUMBER

D

48A4

(NEED TO ADD 2 GND TP) APPLE INC.

SCALE

SHT NONE

8

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051-7537

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"S0,S0M" RAILS =PPVCORE_S0_CPU_REG (CPU VCORE PWR)

PPVCORE_S0_CPU

58B8

=PP5VRT_S0_REG

=PPVCORE_S0_CPU =PPVCORE_S0_CPU_VSENSE

PP5VRT_S0

=PP5V_S0_HDD =PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT

11B5 11D6 12D6 43D8

D

=PP5V_S0_CPU_IMVP =PPCPUVTT_S0_REG

65A6 62C2

PPCPUVTT_S0

=PP5V_S0_ODD =PP5V_S0_KBDLED =PP5V_S0_DP_AUX_MUX =PP5V_S0_CPUVTTS0

7D3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_SMC_LS

61C1 44D8

=PPMCPCORE_S0_REG

=PP1V5_S3_REG

PP1V5_S3

(MCP VCORE REG. OUTPUT)

46C5

36D5 65D6

=PP3V3_S3_FET

PP3V3_S3

65D3 28D7 29D7 30C6

67B6 62C8

=PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_PDCISENS =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS

6D8 10D5 11C6 12B6 13D6

40D3

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

42D3 59B3 42B5 27D8 31A6 21A3

47A6 47B5 47C5 47D2 49B7 49D6

a n i

43D8

=PP5VLT_S3_REG

PP5VLT_S3

7D3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

=PPVCORE_S0_MCP

PPVCORE_S0_MCP

(MCP VCORE AFTER SENSE RES)

C 59C8

=PP0V75_S0_REG

7D3


PP0V75_S0

65C6

=PP3V3_S0_FET

=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_ODD =PP3V3_S0_LPCPLUS =PP3V3_S0_SMBUS_SMC_0_S0 =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO

7D3

65B3 28A4 29A4

=PP3V3_S0_IMVP 65A5

=PP1V05_S0_FET

PP1V05_S0

=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON

44C8

=PP1V5_S0_FET

=PP3V3_S0_MCP_PLL_UF

8A8 24D8

=PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP5VR3V3_S0_MCPCOREISNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_VMON =PP3V3_S0_MCPDDRISNS =PP3V3_S0_CPUVTTISNS =PPVIN_S0_P1V8S0 =PP3V3_FC_CON =PP3V3_S0_TPAD =PP3V3_S0_SMBUS_MCP_1

24D4 24C4 8A8 24D6 18A6 25D7 64A8

PP1V5_S0_R

=PP1V5_S0_FET_R

(DDR PWR REG. OUTPUT)


=PP1V5_S0_CPU =PP1V5_S0_VMON =PP1V5_FC_CON

e r

11B6 12B6 64A8 32C3

B =PP1V5_S0 (DDR PWR AFTER SENSE RES.) 44C7

PP1V5_S0

7D3


=PP1V8R1V5_S0_MCP_MEM =PP1V5_S0_MEM_MCP

63C2

=PP1V8_S0_REG

PP1V8_S0

16C3 16C7 24C8 29B3

P 7D3

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

18B6 25D7

PEX & SATA AVDD/DVDD aliases 24D1

=PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1

PP1V05_S0_MCP_PEX_AVDD MAKE_BASE=TRUE

206 mA (A01)

A

24D8 8B7

=PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_DVDD 206 mA (A01)

24C2

=PP1V05_S0_MCP_SATA_AVDD0 =PP1V05_S0_MCP_SATA_AVDD1

PP1V05_S0_MCP_SATA_AVDD MAKE_BASE=TRUE

6D8 13D6 21C2 22B3 24B8 25D4 25B7 36B7 36D5 41C3 42D5 42C3 42D8 46C5 51A7 51D8 52D6 54D8 55B5

m il

=PP3V3_S0_LCD =PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM

7D3


65D1

=PP5V_S3_EXTUSB =PP5V_S3_IR =PP5V_S3_BTCAMERA =PP5V_S3_VTTCLAMP =PP5V_S3_MCPDDRFET =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_WLAN =PP5V_S3_1V5S30V75S0 =PP5V_S3_AUDIO =PP5V_S3_AUDIO_AMP =PP5V_S3_P1V05S0FET

7D3



=PPVTT_S0_VTTCLAMP =PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B

PP3V3_S0

60D8 66C5

59D7 27D3

=PPVTT_S3_DDR_BUF

18C1 19D1 21A4 25B8

24B6

21D3 21D8 24A8

40A1 40D2 45C6 45D6 44D7

37C7

56D1 56B8

57C1

=PP18V5_DCIN_CONN

=PPBUS_G3H

38B4 38D7 31B3 65A3

65D4

40B8 48C8 31C1 59C5

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_DVDD1

127 mA (A01)

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PP3V42_G3H_RTC_D =PP3V42_G3H_BMON_ISNS

40B8 42C5 64B3 64D3 64D8 57A8 57C6 57D5

47B3 47B5 47C2 47C5 56A3 56B3 39D4 40C1 40C7 40D8 49D7 41B7 41C3 41C7 41D5 26D8 44A8

PP18V5_G3H MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PP18V5_G3H_CHGR

57D8

PPBUS_G3H

7C3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT =PPVIN_S0_MCPCORES0 =PPVIN_S0_MCPREG_VIN =PPVIN_S5_1V5S30V75S0 =PPVIN_S5_3V3S5 =PPVIN_S0_5VRTS0 =PPVIN_S3_5VLTS3 =PPBUS_G3HRS5 =PPCPUVCORE_VTT_ISNS_R

70D8 61C3 61C6 59C2 58B3 58B6 58C6

C

61D8 43B8 44B8

44B7

=PPCPUVCORE_VTT_ISNS

PPBUS_G3H_CPU_ISNS MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE

(AFTER HIGH SIDE CPU VCORE & CPU VTT SENSING RES.)

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

PPVTT_S3_DDR_BUF


62C6 60C2 60D4 60D8

"ENET" RAILS 34D2

=PP3V3_ENET_FET

PP3V3_ENET_PHY MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE

7C3

=PP3V3_ENET_MCP_RMGT

18C7 18D3 24A6 24B6

29A8

=PP3V3_ENET_PHY

64A5 64B8 44C7

"S5" RAILS 34B2

44B7

=PP1V05_ENET_FET

PP1V2R1V05_ENET

63B4

=PP1V05_S5_REG

48A6 42C8

58B1

=PP3V3_S5_REG

7C3


63C5 32C3

33D7

PP1V1R1V05_S5

7C3

=PP1V05_ENET_MCP_PLL_MAC



=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET

34C4

PP3V3_S5

7C3

=PP1V05_ENET_PHY

22A3 24C8

B

24A8

18D3 24C6

33D2

65B6


=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S5_LCD =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_SMBUS_MCP_1 =PP3V3_S5_MCP_A01 =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P1V05S5 =PP3V3_S5_P1V05FET =PP3V3_S5_MEMRESET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR

206 mA (A01)

17B6

57 mA (A01) 17A6

127 mA (A01)

18C7 20C1 41B5 41C7 50C6 66C8 22B3 24B8 26B8 42C7 23C4 41B4 64B3 64C4 34C5 65D8 65C8

Power Aliases

63B7 65A8

SYNC_MASTER=BEN

A

30C6


34D5 68D8


20A6


43 mA (A01)


20B6

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

8

D

37B8 38B4

53B8 53C8 53D8

28A8

17A3

20B6

=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_LIDSWITCH =PP3V42_G3H_TPAD =PP3V42_G3H_BATT

65B8

127 mA (A01) 24D6 8B7

7A7 7B5 7C3

(BEFORE HIGH SIDE SENSING RES.)

51A7 55D4

68A8 68B8

17B3

20B6

y r

7B5 7D3


48A5

61C8

44D7 22D5 24D8 61B1

PP3V42_G3H

60D8

9C2 14A2 14B7 22D3 24C8

=PPVCORE_S0_MCP_VSENSE

=PP3V42_G3H_REG


=PP1V5_S3_P1V5S0FET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET

36A5 41D5

PPVCORE_S0_MCP_R

=PPVCORE_S0_MCP_REG_R

56B4

7D3


7D3 7D7

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

7D3


1

"G3H" RAILS

"S3" RAILS 59B1

60D1

2

3

4

5

A

OF 8

1

109

8

6

7 HEATSINK STANDOFFS

STDOFF-4.5OD.98H-1.1-3.48-TH

UNUSED GPU LANES =PEG_D2R_N NC_PEG_D2R_N

17D6 17C6

=PEG_D2R_P

NC_PEG_D2R_P

17D3 17C3

=PEG_R2D_C_N

NC_PEG_R2D_C_N

NO_TEST=TRUE

Z0901

Z0902

17D6 17C6

STDOFF-4.5OD.98H-1.1-3.48-TH

NO_TEST=TRUE

1

1

NO_TEST=TRUE 17D3 17C3

ABOVE CPU

17C6

TP_PEG_PRSNT_L

17C3

D

Z0904

Z0903

17C3

MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT

NC_MCP_CLK27M_XTALOUT

CRT_IG_R_C_PR

NC_CRT_IG_R_C_PR

NO_TEST=TRUE NO_TEST=TRUE

17B6

PCIE_FW_D2R_P

TP_PCIE_FW_D2R_P

PCIE_FW_D2R_N

TP_PCIE_FW_D2R_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CRT_IG_B_COMP_PB

NC_CRT_IG_B_COMP_PB

18B3

CRT_IG_HSYNC

NC_CRT_IG_HSYNC

18B3

ETHERNET ALIASES

MAKE_BASE=TRUE

18C3

NO_TEST=TRUE

17B6

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y NO_TEST=TRUE

MAKE_BASE=TRUE

CRT_IG_VSYNC

34C5

MAKE_BASE=TRUE 34B5

MAKE_BASE=TRUE

NO_TEST=TRUE

33C2

MAKE_BASE=TRUE

33C6

MAKE_BASE=TRUE

PCIE_FW_R2D_C_P

TP_PCIE_FW_R2D_C_P

17B3

PCIE_FW_R2D_C_N

TP_PCIE_FW_R2D_C_N

LVDS ALIASES

MAKE_BASE=TRUE

18B3

UNUSED LVDS SIGNALS LVDS_IG_A_DATA_P NC_LVDS_IG_A_DATA_P3

18B3

LVDS_IG_A_DATA_N

MAKE_BASE=TRUE

FAN STANDOFF

17C6

PCIE_FW_PRSNT_L

TP_PCIE_FW_PRSNT_L

NO_TEST=TRUE

MAKE_BASE=TRUE 17C6

Z0905

FW_CLKREQ_L

TP_FW_CLKREQ_L

STDOFF-4.5OD.98H-1.1-3.48-TH

17C3

PCIE_CLK100M_FW_P

TP_PCIE_CLK100M_FW_P

17C3

PCIE_CLK100M_FW_N

TP_PCIE_CLK100M_FW_N

18B3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

LVDS_IG_B_CLK_P

18B3

LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_N

a n i NO_TEST=TRUE

MAKE_BASE=TRUE 18B3

LVDS_IG_B_DATA_P

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P NO_TEST=TRUE

UNUSED EXPRESS CARD LANE

18B3

LVDS_IG_B_DATA_N

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N NO_TEST=TRUE

17B6

TP_PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE 17B6

TP_PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

AUDIO CHASSIS GND

17B3

PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_R2D_C_P

17B3

PCIE_EXCARD_R2D_C_N

TP_PCIE_EXCARD_R2D_C_N

17C6

PCIE_EXCARD_PRSNT_L

TP_PCIE_EXCARD_PRSNT_L

OMIT

MAKE_BASE=TRUE

C

55A4 54A3

=GND_CHASSIS_AUDIO_JACK =GND_CHASSIS_AUDIO_MIC

17C6

EXCARD_CLKREQ_L

TP_EXCARD_CLKREQ_L

14B6

MAKE_BASE=TRUE

Z0906 TH

19B7

SL-3.10X2.70

TP_PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE 17C3

TP_GMUX_JTAG_TCK_L MAKE_BASE=TRUE TP_GMUX_JTAG_TDO

19D4

GMUX_JTAG_TDI

TP_GMUX_JTAG_TDI

19D4

GMUX_JTAG_TMS

AIRPORT CARD PRESENT SIGNAL

MLB MOUNTING SCREW HOLES OMIT Z0909 3R2P5

OMIT Z0908 3R2P5 1

1

PCIE_MINI_PRSNT_L 18D6

FOR VENICE CARD 17B6

TP_PE4_CLKREQ_L

18C6

FC_CLKREQ_L

17B6

=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS

m il 32C5

MAKE_BASE=TRUE

1

TP_PE4_PRSNT_L

FC_PRSNT_L

18C6

32B3

MAKE_BASE=TRUE

17B3

TP_PCIE_CLK100M_PE4P

17B3

TP_PCIE_CLK100M_PE4N

17B6

TP_PCIE_PE4_D2RP

17B6

TP_PCIE_PE4_D2RN

PCIE_CLK100M_FC_P

32C5 73D3

MAKE_BASE=TRUE

OMIT Z0911 3R2P5

OMIT Z0912 3R2P5

1

OMIT Z0913 3R2P5

1

PCIE_CLK100M_FC_N

32B5 73D3

MAKE_BASE=TRUE

1

18B6

PCIE_FC_D2R_N

=DVI_HPD_GMUX_INT

32B5 73D3

MAKE_BASE=TRUE

17B3

TP_PCIE_PE4_R2D_CP

PCIE_FC_R2D_C_P

32C6 73D3

MAKE_BASE=TRUE

17B3

TP_PCIE_PE4_R2D_CN

PCIE_FC_R2D_C_N

32C6 73D3

MAKE_BASE=TRUE

e r

VENICE BOARD STANDOFFS VENICE

Z0914

B

STDOFF-4.0OD3.0H-TH

VENICE

VENICE

Z0915

STDOFF-4.0OD3.0H-TH

1

STDOFF-4.0OD3.0H-TH

20C3

20C3

20D3

20D3

20C3 20C3

20D3

EMI IO POGO PINS ZS0901

1.4DIA-SHORT-EMI-MLB-M97-M98 SM 1

TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXCARD_P TP_USB_EXCARD_N

=MCP_BSEL

Extra FSB Pull-ups

24C8 22D3 14B7 14A2 8D7

=PP1V05_S0_MCP_FSB

C

MCP_A01&MCP_A01P&MCP_A01Q

NO STUFF

R0970 1

R0990 1

220

200

150

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

NO STUFF 1

R0930

1

NO STUFF 1

R0960 62

47K

71B3 60C7 14A3 10B2

OUT

71C3 14B6 10D6

OUT

71C3 14A3 13B2 10D6

OUT

71C3 14A3 10B8

OUT

71C3 14A3 10B8

OUT

MAKE_BASE=TRUE

R0980 150

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

R0940 20K

NO STUFF

R0950 1

MAKE_BASE=TRUE

1

266 133 200 (166) 333 100 (400) (RSVD)

Exist in MRB but not Intel designs. Here for CYA. If found to be necessary, will move to page14.csa

MCP_MII_PD

HPLUG_DET2

14A7

OUT

FSB MHZ

0 1 0 1 0 1 0 1

5% 1/16W MF-LF 2 402

CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI

5% 1/16W MF-LF 2 402

B

TP_USB_MINI_P

USB_MINI_P USB_MINI_N

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_USB_MINI_N

MAKE_BASE=TRUE

ZS0903

1.4DIA-SHORT-EMI-MLB-M97-M98


SM

SM

1

SM

1

SIGNAL ALIAS

ZS0904

ZS0905

ZS0906

ZS0907

2.0DIA-TALL-EMI-MLB-M97-M98



SM

SM

SM

SM

1

CPU_BSEL MAKE_BASE=TRUE

0 0 1 1 0 0 1 1

MAKE_BASE=TRUE

2.0DIA-TALL-EMI-MLB-M97-M98 1

IN

0 0 0 0 1 1 1 1

MAKE_BASE=TRUE


EMI POGO PINS

A

P

20D3

USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_EXCARD_P USB_EXCARD_N

ZS0902

1

71C3 10B4 10A4

BSEL

UNUSED USB PORTS

1

ZS0900

MAKE_BASE=TRUE MAKE_BASE=TRUE

USB ALIASES

Z0916

1

MAKE_BASE=TRUE

DP HOTPLUG PULL-DOWN

32C5 73C3

MAKE_BASE=TRUE

PCIE_FC_D2R_P

MAKE_BASE=TRUE

D

21C3

MAKE_BASE=TRUE

TP_PP3V3_ENET_PHY_VDDREG MAKE_BASE=TRUE NC_RTL8211_REGOUT

LAN ALIASES

MAKE_BASE=TRUE

OMIT Z0910 3R2P5

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

MAKE_BASE=TRUE

31D7 17C6

MAKE_BASE=TRUE

GMUX_JTAG_TCK_L GMUX_JTAG_TDO

TP_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_N

TP_CPU_PECI_MCP TP_FW_PME_L

17B6

17B6

MAKE_BASE=TRUE 17C3

CPU_PECI_MCP FW_PME_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

1 54B8 54A8

MISC MCP79 ALIASES

MAKE_BASE=TRUE

GND_CHASSIS_AUDIO

MAKE_BASE=TRUE

PM_SLP_RMGT_L

CPU FSB FREQUENCY STRAPS

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_P NO_TEST=TRUE

MAKE_BASE=TRUE

1

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N3 NO_TEST=TRUE

MAKE_BASE=TRUE

=P3V3ENET_EN =P1V05ENET_EN =PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT =RTL8211_ENSWREG

y r 33C2

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

17B3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

18C6

CRT_IG_G_Y_Y

TP_MEM_A_A15 TP_MEM_B_A15

NC_MCP_CLK27M_XTALIN

18C3

UNUSED FW LANE

BELOW CPU

29C5

MEM_A_A MEM_B_A

MAKE_BASE=TRUE

MAKE_BASE=TRUE

18C3

28C5

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

BELOW MCP

UNUSED ADDRESS PINS

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_PEG_CLK100M_N

1

1

18C6

TP_PEG_CLK100M_P

PEG_CLK100M_N

MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

PEG_CLK100M_P

18C6

NO_TEST=TRUE

MAKE_BASE=TRUE

PEG_PRSNT_L

18C6

1

SO-DIMM ALIASES

UNUSED CRT & TV-OUT INTERFACE MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_C_P NO_TEST=TRUE

LEFT OF CPU

DACS ALIASES

MAKE_BASE=TRUE

=PEG_R2D_C_P

2

3

4

5 PCI-E ALIASES

1

SYNC_MASTER=M97_MLB

A


1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 9

1

109

8

6

7

2

3

4

5

1

OMIT

71D3 14C6

BI

71D3 14C6

BI

71D3 14C6

BI

71D3 14C6

BI

71D3 14C6

BI

71D3 14C6

BI

71D3 14C6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6 71C3 14C6

BI BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

C

BI

71C3 14B6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14C6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14B6

BI

71C3 14A3 71C3 14B7 71C3 14A3

K3

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L

Y2

IN CPU_A20M_L OUT CPU_FERR_L IN CPU_IGNNE_L

71B3 14A3

IN

71C3 14A3 9B2

IN

71C3 14A3 9B2

IN

71B3 14A3

FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L

IN

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

H2 K2 J3 L1

U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1

A6 A5 C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 F6 D2 D22 D3

FCBGA

1 OF 4

REQ0* REQ1* REQ2* REQ3* REQ4*

A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*

G5

DEFER* DRDY* DBSY*

H5

E1

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

BR0*

F1

FSB_BREQ0_L

F21

BI

14B6 71C3

BI

14B6 71C3

BI

14B3 71C3

BI

14B3 71C3

BI

14B6 71C3

BI

14B6 71C3

BI

9B2 14B6 71C3

IN

LOCK*

H4

FSB_LOCK_L

BI

RESET* RS0* RS1* RS2* TRDY*

C1

FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L

D20

BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*

F3 F4 G3 G2

71B3

FSB_HIT_L FSB_HITM_L

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

=PP1V05_S0_CPU

6D8 8D7 11C6 12B6 13D6

R1000 1 54.9 1% 1/16W MF-LF 402

2

D

B3

CPU_IERR_L CPU_INIT_L

IERR* INIT*

HIT* HITM*

XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

14A3 71C3

IN

9B2 13B2 14A3 71C3

IN

14A6 71C3

IN

14A6 71C3

IN

14A6 71C3

IN

14B6 71C3

BI

14B6 71C3

BI

14B6 71C3

BI

OMIT

13C6 71A3

BI

13C6 71A3

BI

13C6 71A3

BI

13C6 71A3

BI

R1001 1

13C6 71A3

2 13C6 71A3

BI

THERMTRIP*

RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8

BI

71D3 14D3

BI

71D3 14D3

BI BI

6C4 10B6 71A3

71D3 14D3

IN

6C6 6C7 10B6 13B3 71A3

71D3 14D3

BI

IN

6C6 6C7 10A6 13B3 71A3

71D3 14D3

BI

71D3 14D3

BI

OUT

13B3 26A3

R1002 1

OUT

45D5 77D3

B25

OUT

45D5 77D3

C7

PM_THRMTRIP_L

OUT

14B7 40C4 71B3

71D3 14D3

2

OUT

14B6 40D4 60C8 71B3

A21

FSB_CLK_CPU_P FSB_CLK_CPU_N

BI

71D3 14D3

BI

71D3 14D6

BI

71D3 14D6

BI

71D3 14D6

BI

71D3 14D3

BI

71D3 14D3

BI

e r 1K

CPU JTAG Support

B

R1090

71A3 13B3 10C6 6C7 6C6

XDP_TMS

1

71A3 13B3 10C6 6C6

XDP_TDI

XDP_TDO

1

P 71A3 10C6 6C4

71A3 13B3 10C6 6C7 6C6

XDP_TCK

XDP_TRST_L

R1006 2.0K

R1092 54.9

1

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

71A3 13B6 10C6 6C7 6C6

1

2

1% 1/16W MF-LF 402

2

1% 1/16W MF-LF 402

2

1% 1/16W MF-LF 402

R1091 54.9

54.9

R1005

2

1% 1/16W MF-LF 402

1% 1/16W MF-LF 2 402

1

R1094

1

649

BI

71D3 14C3

BI

71D3 14C3

BI

54.9 1% 1/16W MF-LF 402

2

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14C3

BI

71D3 14D6

BI

71D3 14D6

BI

71D3 14D6

BI

a n i

FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_DSTB_L_N FSB_DSTB_L_P FSB_DINV_L

CPU_GTLREF CPU_TEST1 CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6 TP_CPU_TEST7 OUT CPU_BSEL OUT CPU_BSEL OUT CPU_BSEL

71B3 27B1

NO STUFF

C1014 10% 16V X5R 402

R1010 1

0 5% 1/16W MF-LF 402

R1011 1 1K

2

NO STUFF 1

2

71C3 9C2 71C3 9C2 71C3 9C2

E22 F24 E26 G22 F23

G25 E25

E23 K24 G24 J24 J23 H22 F26 K22 H23 J26

H26

H25

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26

M26 N24

AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21

D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*

D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2

U1000 PENRYN FCBGA

2 OF 4

D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*

D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3

MISC

DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*


Y22

AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25

AA23 AA24 AB25 Y26

AA26 U22


AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25

AF24 AC20

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14C3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14D6 71D3

BI

14D6 71D3

BI

14D6 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14B3 71D3

BI

14D6 71D3

BI

14D6 71D3

BI

14D6 71D3

C

B

R26 71A3 CPU_COMP U26 71A3 CPU_COMP AA1 71A3 CPU_COMP Y1

E5 B5 D24 D6 D7 AE6

71B3

CPU_COMP CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L

IN

9B2 14A3 60C7 71B3

IN

14A3 71B3

R1021 1

54.9

IN

14A3 71B3

IN

13C7 14A3 71B3

IN

14A3 71B3

OUT

R1023 1 1% 1/16W MF-LF 402

54.9 1% 1/16W MF-LF 402

2

60C7

1

5% 1/16W MF-LF 2 402

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

2

2

R1020 27.4

1% 1/16W MF-LF 402

2

1% 1/16W MF-LF 402

Place within 12.7mm of CPU

CPU FSB SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

7

1

R1022

PLACEMENT_NOTE (all 4 resistors):

1% 1/16W MF-LF 402

SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL

8

2

27.4

R1012 1K

5% 1/16W MF-LF 402 2

1

0.1uF

NO STUFF

NO STUFF

R1093

BI

71D3 14C3

71D3 14C3

14B3 71B3

IN

BI


m il

14B3 71B3

IN

BI

71D3 14D3

71D3 14D3

A22

BI

71D3 14D3

1

A

BI

71D3 14D3

6C6 10B6 13B3 71A3

H CLK

BCLK0 BCLK1

BI

71D3 14D3

IN

CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N

A24

BI

IN

5% 1/16W MF-LF 402 D21

71D3 14D3

71D3 14D3

THERMAL PROCHOT* THERMDA THERMDC

BI

71D3 14D3

54.9 1% 1/16W MF-LF 402

71D3 14D3

6C6 6C7 10A6 13B6 71A3

OUT

y r

14B6 71C3

68

A20M* FERR* IGNNE* STPCLK* LINT0 LINT1 SMI*

FSB_ADS_L FSB_BNR_L FSB_BPRI_L

H1 E2

DATA GRP 2

BI

ADS* BNR* BPRI*

PENRYN

DATA GRP 3

BI

71D3 14C6

M3

U1000

DATA GRP 0

71D3 14C6

K5

A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*

DATA GRP 1

BI

L4

CONTROL

71D3 14C6

L5

XDP/ITP SIGNALS

BI

J4

ADDR GROUP0

BI

71D3 14D6

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADSTB_L

ADDR GROUP1

BI

71D3 14D6

ICH

BI

71D3 14D6

RESERVED

D

71D3 14D6

A

OF 10

1

109

A

8

6

7

5

2

3

4

A4

P6

A8

(CPU CORE POWER)

P21

OMIT

A11

=PPVCORE_S0_CPU

D

A7

AB20

A9

OMIT

AB7

U1000

AC7

A10 A12

FCBGA

A15

(SV (SV (SV (LV

Design Target) HFM) LFM) Design Target)

3 OF 4

A14

U1000

A16

PENRYN

R25 T1

B13

AC15

B16

AC17

B19

AC18

B21

B7

AD7

B24

B9

AD9

C5

B10

AD10

C8

B12

AD12

C11

B14

AD14

C14

B15

AD15

B17

AD17

B18

AD18

B20

AE9

AE12

C12

AE13

C13

AE15

C15

AE17

C17

AE18

C18

AE20

AF10

D12

AF12

D14

AF14

D15

AF15

VCC

D17

AF17

D18

AF18 AF20

E12

V6

E13

J6

E15

K6

E17

M6

E18

J21

E20

K21

F7

M21

VCCP

F10

N6

F12

R21

F14

R6

F15

T21

F17

T6

F18

V21

F20

W21

AA7

VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6

AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14

VCCSENSE

AB15 AB17 AB18

VSSSENSE

A

AF5 AE5 AF4 AE3 AF3 AE2

a n i D11 D13 D16 D19 D23 D26

(CPU IO POWER 1.05V)

m il

4500 mA (before VCC stable) 2500 mA (after VCC stable)

e r

(CPU INTERNAL PLL POWER 1.5V) 8B7 12B6

130 mA

CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID CPU_VID

OUT

AE7

CPU_VCCSENSE_P

CPU_VCCSENSE_N

60C7 71A3

OUT

60C7 71A3

OUT

60C7 71A3

OUT

60C7 71A3

OUT

60C7 71A3

OUT

60C7 71A3

OUT

60C7 71A3

=PPVCORE_S0_CPU

1

R1100 100

2

1% 1/16W MF-LF 402

OUT

8D7 11D6 12D6

60A5 71A3

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs. PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

2

W23 W26 Y3 Y6

Y21 Y24 AA2 AA5 AA8

AA11 AA14

AA19

E6

AA25

E8

AB1

VSS

VSS

AB4 AB8

E16

AB11

E19

AB13

E21

AB16

E24

AB19

F5

AB23

F8

AB26

F11

AC3

F13

AC6

F16

AC8

F19

AC11

F2

AC14

F22

AC16

F25

AC19

G4

AC21

G1

AC24

G23

AD2

G26

AD5

H3

AD8

H6

AD11

H21

AD13

H24

AD16

J2

AD19

J5

AD22

J22

AD25

J25

AE1

K1

AE4

K4

AE8

K23

AE11

K26

AE14

L3

AE16

L6

AE19

L21

AE23

L24

AE26 A2

M5

AF6

R1101

M22

AF8

100

M25

AF11

N1

AF13

60A5 71A3

1% 1/16W MF-LF 402

N4

AF16

N23

AF19

N26

AF21

P3 B1

C

AA16

M2

OUT

1

W4

AA22

E14

6D8 8D7 10D5 12B6 13D6

W1

E3

E11

P AF7

V25

D4

C26

AD6

V22

D8

AA12 AA13

V5

D1

B26

AA10

V2

C25

=PP1V5_S0_CPU

(BR1#)

AA9

U24

C22

N21

F9

U21

C2

G21

E10

U6

C19

=PP1V05_S0_CPU

E9

y r T23

T26

U3

C16

AF9

D10

D

T4

B8 B11

AE10

R22

B6

AC13

C9

R5

4 OF 4

AF2

AC12

C10

R2

A23

A20

VCC

P24

FCBGA A19

A18

E7

B

A A A A

A17

D9

C

44 41 30.4 23

AC9

PENRYN

A13

8D7 11B5 12D6

1

B

A25

(Socket-P KEY)

AF25

CPU Power & Ground SYNC_MASTER=T18_MLB



SYNC FROM T18 CHANGE CPU FROM SOCKET TO BGA SYMBOL


DRAWING NUMBER

D APPLE INC.

8

SCALE

SHT NONE

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

7

6

5

4

3

2

REV.

051-7537

A

OF 11

1

109

A

8

6

7

2

3

4

5

1

CPU VCore HF and Bulk Decoupling 4X 330UF. 20X 22UF 0805 PLACEMENT_NOTE (C1200-C1219): 11D6 11B5 8D7

=PPVCORE_S0_CPU Place inside socket cavity on secondary side.

D

CRITICAL 1

CRITICAL 1

C1200 22UF

2

22UF

20% 6.3V CERM-X5R 805

2

CRITICAL 1

1

2

2

C1203

1

20% 6.3V CERM-X5R 805

2

C1213

1

2

20% 6.3V CERM-X5R 805

2

2

CRITICAL 1

1

2

C1215

2

20% 6.3V CERM-X5R 805

2

Place on secondary side. CRITICAL

CRITICAL 1

330UF 3

2

CRITICAL 1

C1241 330UF

20% 2.0V POLY-TANT D2T-SM2

3

2

CRITICAL 1

C1242 330UF

C1243 330UF

20% 6.3V CERM-X5R 805

CRITICAL 1

22UF 2

20% 6.3V CERM-X5R 805

22UF 2

CRITICAL 1

C1217

2

20% 6.3V CERM-X5R 805

2

y r

20% 6.3V CERM-X5R 805

CRITICAL

C1218

1

22UF 2

C1209 22UF

20% 6.3V CERM-X5R 805

CRITICAL 1

22UF

D

CRITICAL 1

C1208

C1219 22UF

20% 6.3V CERM-X5R 805

2

20% 6.3V CERM-X5R 805

C

m il


3

2


3


2

VCCA (CPU AVdd) DECOUPLING 1x 10uF, 1x 0.01uF 11B6 8B7

C1216

C1207

a n i

PLACEMENT_NOTE (C1240-C1243):

C1240

20% 6.3V CERM-X5R 805

22UF

C

1

CRITICAL 1

CRITICAL 1

22UF

20% 6.3V CERM-X5R 805

C1206 22UF

20% 6.3V CERM-X5R 805

CRITICAL

C1214 22UF

2

C1205 22UF

20% 6.3V CERM-X5R 805

CRITICAL 1

22UF

20% 6.3V CERM-X5R 805

CRITICAL 1

C1204 22UF

2

CRITICAL

C1212 22UF

20% 6.3V CERM-X5R 805

CRITICAL 1

22UF

20% 6.3V CERM-X5R 805

CRITICAL

C1211 22UF

20% 6.3V CERM-X5R 805

CRITICAL 1

C1202 22UF

20% 6.3V CERM-X5R 805

CRITICAL

C1210 22UF

2

CRITICAL 1

C1201

=PP1V5_S0_CPU

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

C1250

1

1

C1251

e r 10uF 20% 6.3V X5R 603

B

0.01UF

2

10% 16V CERM 402

2

B

VCCP (CPU I/O) DECOUPLING 1x 330uF, 6x 0.1uF 0402

13D6 11C6 10D5 8D7 6D8

=PP1V05_S0_CPU

PLACEMENT_NOTE=Place C1260 between CPU & NB.

P

A

CRITICAL

C1260

1

1

330UF


2

3

2

C1261

1

C1262

1

C1263

1

C1264

1

C1265

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

2

2

2

2

1

C1266 0.1UF

2

20% 10V CERM 402

CPU Decoupling SYNC_MASTER=RAYMOND


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231 REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 12

1

109

A

8

6

7

2

3

4

5

1

D

D

y r

MCP79-specific pinout 8C5 6D8 12B6 11C6 10D5 8D7 6D8

=PP3V3_S0_XDP =PP1V05_S0_CPU

XDP_CONN CRITICAL

J1300 6-1747769-0

XDP

F-ST-SM

R1315 1

62

1% 1/16W MF-LF 402 2

71A3 10C5

BI

71A3 10C6

BI

71A3 10C6

BI

71A3 10C6

IN

71A3 10C6

IN

71A3 10C6

IN

C

XDP_BPM_L XDP_BPM_L

OBSFN_A0 OBSFN_A1

XDP_BPM_L XDP_BPM_L

OBSDATA_A0 OBSDATA_A1

XDP_BPM_L XDP_BPM_L

OBSDATA_A2 OBSDATA_A3

TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1

OBSFN_B0 OBSFN_B1

TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1

OBSDATA_B0 OBSDATA_B1

TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3

XDP

OBSDATA_B2 OBSDATA_B3

71B3 14A3 10B2

IN

CPU_PWRGD

1

XDP_PWRGD

2

XDP_OBS20

5% 1/16W MF-LF 402 23C5 19C4

IN

21B7 6C5

OUT

74B3 42D8 21C3

BI

74B3 42D8 21C3

BI

71A3 10C6 10A6 6C7 6C6

OUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

OBSFN_C0 OBSFN_C1

PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK

PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0

NC

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

e r

B

P

A

1

1

61

0.1uF 10% 16V X5R 402

IN

OUT

6C3

6C5 21B7

MCP_DEBUG MCP_DEBUG

BI

19D7 74D3

BI

19D7 74D3

OBSDATA_C2 OBSDATA_C3

MCP_DEBUG MCP_DEBUG

BI

19D7 74D3

OBSFN_D0 OBSFN_D1

JTAG_MCP_TDI JTAG_MCP_TMS

OUT

6C5 21B7 23C5

OUT

6C5 21B7 23C5

OBSDATA_D0 OBSDATA_D1

MCP_DEBUG MCP_DEBUG

BI

19D7 74D3

BI

19D7 74D3

OBSDATA_D2 OBSDATA_D3

MCP_DEBUG MCP_DEBUG

BI

19D7 74D3

BI

19D7 74D3

FSB_CLK_ITP_P ITPCLK/HOOK4 FSB_CLK_ITP_N ITPCLK#/HOOK5 VCC_OBS_CD 71A3 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. XDP_TDO_CONN TDO XDP_TRST_L TRSTn XDP_TDI TDI XDP_TMS TMS XDP_PRESENT# XDP

XDP

C1300

JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L

OBSDATA_C0 OBSDATA_C1

m il

R1399 1K

a n i

64

54.9

BI

19D7 74D3

IN

14A3 71B3

IN

14A3 71B3

OUT

10C6 26A3

IN

C

XDP

R1303 1

1K 5% 1/16W MF-LF 402

2

FSB_CPURST_L

IN

9B2 10D6 14A3 71C3

PLACEMENT_NOTE=Place close to CPU to minimize stub.

6C3

OUT

6C6 6C7 10A6 10C6 71A3

OUT

6C6 10B6 10C6 71A3

OUT

6C6 6C7 10B6 10C6 71A3

C1301 0.1uF

63

2

516S0625

2

10% 16V X5R 402

B

eXtended Debug Port (XDP) SYNC_MASTER=T18_MLB



SYNC FROM T18 CHANGE STANDARD XDP CONNECTOR TO SMALLER ONE 516S0625 RENAME JTAG_MCP_TDO TO JTAG_MCP_TDO_CONN RENAME XDP_TDO TO XDP_TDO_CONN


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 13

1

109

A

8

6

7

2

3

4

5

1

OMIT

U1400 MCP79-TOPO-B BGA (1 OF 11)

BI

71D3 10C4

BI

71D3 10C4

71D3 10B4

D

C

71D3 10B4

BI

71D3 10C2

BI

71D3 10C2

BI

71D3 10C2

BI

71D3 10B2

BI

71D3 10B2

BI

71D3 10B2

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71D3 10D8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

BI

71C3 10C8

71C3 10D8

R1410 1

B 71B3 40C4 10C6 71C3 10C8

IN IN

R1415 1

54.9

62

1% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

1

2

71C3 10D8

BI

71C3 10D6 71C3 10D6

71C3 10D6 9B2

71C3 10D6 71C3 10D6 71C3 10C6 71C3 10C6

71C3 10D6

71C3 10D6

R1420

9C1

IN

9C1

IN

9C1

IN

=MCP_BSEL =MCP_BSEL =MCP_BSEL

1

NO STUFF

R1421

1K

1K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

NO STUFF

P

1

1

R1422

2

2

5% 1/16W MF-LF 402

R1430

A

9C4

1

1

R1435

49.9

49.9

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

2

2

BI

1

OUT

FSB_DSTB_L_P FSB_DSTB_L_N FSB_DINV_L

M39

V35

L36 N35

M41 J41

AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34

CPU_PECI_MCP CPU_PROCHOT_L

71C3 10D6

OUT

71C3 10D6

OUT

71C3 10D6

OUT

24C2

AL35 AN34 AR39 AN35 AE36 AK35

AC38 AA33 AC39 AC33 AC35

AD42 AD43 AE40 AL32

AD39 AD41 AB42 AD40 AC43 AE41

E41

AJ41 AG43 AH40

F42

71B3

D42 F41

49.9 1% 1/16W MF-LF 402

CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1# CPU_DSTBP2# CPU_DSTBN2# CPU_DBI2# CPU_DSTBP3# CPU_DSTBN3# CPU_DBI3# CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35#

CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#

FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L

Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36

AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39

CPU_ADSTB0# CPU_ADSTB1# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY#

CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR# CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

CPU_BPRI# CPU_DEFER#

N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43

AA41

AA40

BCLK_OUT_CPU_P BCLK_OUT_CPU_N

G42

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

AL43

BCLK_OUT_NB_P BCLK_OUT_NB_N

AL41

BCLK_IN_N BCLK_IN_P

AK41

G41

AL42

AK42

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10C4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10B4 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10C2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

BI

10B2 71D3

D

y r

a n i

AA34

L38

BI

FSB_BPRI_L FSB_DEFER_L

OUT

10D6 71C3

OUT

10D6 71C3

FSB_CLK_CPU_P FSB_CLK_CPU_N

OUT

10B6 71B3

OUT

10B6 71B3

FSB_CLK_ITP_P FSB_CLK_ITP_N

OUT

13C3 71B3

OUT

13B3 71B3

C

B

FSB_CLK_MCP_P 71B3 FSB_CLK_MCP_N 71B3

Loop-back clock for delay matching.

FSB_RS_L FSB_RS_L FSB_RS_L

AC41 AB41 AC42

CPU_RS0# CPU_RS1# CPU_RS2#

PP1V05_S0_MCP_PLL_FSB

270 mA (A01)

71B3

CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0#

m il AL38

(MCP_BSEL) (MCP_BSEL) (MCP_BSEL)

71B3

1% 1/16W MF-LF 402

2

N37

W37

206 20 29 15

mA mA mA mA

MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND

AG27 AH27 AG28 AH28

AM39 AM40

MCP_CPU_COMP_VCC MCP_CPU_COMP_GND

AM43 AM42

R1436

49.9

2


FSB_ADS_L FSB_BNR_L BI FSB_BREQ0_L BI 71C3 FSB_BREQ1_L FSB_DBSY_L BI FSB_DRDY_L BI FSB_HIT_L BI FSB_HITM_L BI FSB_LOCK_L IN FSB_TRDY_L OUT

71B3

R1431 1

W39

BI

OUT

71B3 60C8 40D4 10C5

1K


FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L

BI

BI

V41

e r

5% 1/16W MF-LF 402

PM_THRMTRIP_L CPU_FERR_L

NO STUFF

BI

BI

U40

FSB_ADSTB_L FSB_ADSTB_L

BI

71C3 10D8

71C3 10D8

R1416 62

2

BI

71C3 10D8

T40

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L

BI

71C3 10C8

71C3 10D8

=PP1V05_S0_MCP_FSB

BI BI

71C3 10C8

24C8 22D3 14A2 9C2 8D7

BI

71D3 10B4

71C3 10C8


FSB

71D3 10C4

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU BCLK_VML_COMP_VDD BCLK_VML_COMP_GND CPU_COMP_VCC CPU_COMP_GND

CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI# CPU_PWRGD CPU_RESET# CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP#

AJ40

AF41 AH39 AH42 AF42 AG41 AH41 AH43 H38 AM33 AN33 AM32 AG42 AN32

CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L

OUT

10C8 71C3

OUT

10C8 71C3

OUT

10D6 71C3

OUT

9B2 10B8 71C3

OUT

9B2 10B8 71C3

OUT

10B8 71B3

=PP1V05_S0_MCP_FSB

R1440 150

2

9B2 10D6 13B2 71C3

OUT

10A2 71B3

OUT

10B2 71B3

OUT

10B2 71B3

OUT

10B8 71B3

OUT

9B2 10B2 60C7 71B3

MCP CPU Interface

5% 1/16W MF-LF 402

OUT OUT

8D7 9C2 14B7 22D3 24C8

NO STUFF 1

SYNC_MASTER=T18_MLB



10B2 13C7 71B3

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

8

7

SCALE

SHT NONE

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

6

5

4

3

2

REV.

051-7537

A

OF 14

1

109

A

6

7

5

2

3

4

OMIT

U1400

MCP79-TOPO-B

MCP79-TOPO-B

BGA

BGA

(2 OF 11)

BI

72D3 28A5

BI

72D3 28A7

D

BI

72D3 28A7

BI

72D3 28A7

BI

72D3 28A5

BI

72D3 28A5

BI

72D3 28B5

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28B7

BI BI

72D3 28B7

BI

72D3 28B5

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B7

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B5

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28B7

BI

72D3 28C2

BI

72D3 28C4

BI

72D3 28C2

BI

72D3 28C2

BI

72D3 28C2

BI

72D3 28C4 72D3 28C4 72D3 28C4

BI BI BI

72D3 28B4

BI

72D3 28B2

BI

72D3 28B4

BI

72D3 28C4

BI

72D3 28B2

BI

72D3 28C2

BI

72D3 28C2

BI

72D3 28B4

BI

72D3 28C4

BI

72D3 28C2

BI

72D3 28C2

B

BI

72D3 28B5

72D3 28B5

C

BI

72D3 28A7

BI

72D3 28C4

BI

72D3 28C2

BI

72D3 28C4

BI

72D3 28C2

BI

72D3 28C4

BI

72D3 28C4

BI

72D3 28C4

BI

72D3 28D2

BI

72D3 28D2

BI

72D3 28C2

BI

72D3 28C2

BI

72D3 28C4

BI

72D3 28D4

BI

72C3 28A7

OUT

72C3 28B5

OUT

72C3 28B7

OUT

72C3 28B5

OUT

72C3 28C2

OUT

72C3 28B4

OUT

72C3 28C2

OUT

72C3 28C4

OUT

MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35

MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM

AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34

A

MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0 MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0

(3 OF 11)

MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

MEMORY PARTITION 0

72D3 28A5

1

OMIT

U1400

MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N

AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39

BI

28A5 72C3

72B3 29A5

BI

BI

28A5 72C3

72B3 29A5

BI

BI

28B7 72C3

72B3 29A7

BI

28B7 72C3

72B3 29A7

BI

BI

28B5 72C3

72B3 29A5

BI

BI

28B5 72C3

72B3 29A7

BI

BI

28B7 72C3

72B3 29A5

BI

BI

28B7 72C3

72B3 29A7

BI

BI

28C4 72C3

72B3 29B7

BI

BI

28C4 72C3

72B3 29B7

BI

28B2 72C3

72B3 29B7

BI

BI

28B2 72C3

72B3 29B5

BI

BI

28C4 72C3

72B3 29B5

BI

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

AV17 AP17 AR17

28C4 72C3

72B3 29B5

BI

28C2 72C3

72B3 29B7

BI

BI

28C2 72C3

72B3 29B5

BI

72B3 29B7

BI

OUT

28C5 72D3

OUT

28C7 72D3

OUT

28C7 72D3

MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0

MEM_A_BA MEM_A_BA MEM_A_BA

AP23 AP19 AW17

MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A

AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19

AV33 BA24

MCLK0A_0_P MCLK0A_0_N

BB20

MCS0A_1# MCS0A_0#

AY24

BC20

AT15

P MODT0A_1 MODT0A_0 MCKE0A_1 MCKE0A_0

AR18

AP15 AV15

AU23 AT23

OUT

28C5 72D3

OUT

OUT

28C5 72D3

OUT

28C7 72D3

OUT

28C7 72D3

OUT

28C5 72D3

OUT

BI

72B3 29B5

BI

72B3 29B5

BI

72B3 29B5

BI

72B3 29B7

BI

72B3 29B5

BI

OUT

28C7 72D3

OUT

28C7 72D3

OUT

28C5 72D3

OUT

28C5 72D3

OUT

28C7 72D3

OUT

28C5 72D3

OUT

m il

28C7 72D3

OUT

28C5 72D3

OUT

28C7 72D3

OUT

28C5 72D3

MEM_A_CLK_P MEM_A_CLK_N

OUT

28C5 72D3

OUT

28C5 72D3


OUT

28C7 72D3

OUT

28C7 72D3

MEM_A_CS_L MEM_A_CS_L MEM_A_ODT MEM_A_ODT MEM_A_CKE MEM_A_CKE

OUT

28C7 72D3

OUT

28C5 72D3

BI

72B3 29B5

BI

72B3 29B7

BI

72B3 29B5

BI

72B3 29B7

BI

72B3 29B5

BI

72B3 29B5

BI

72B3 29B7

28C7 72D3

BI

AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5

MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0

BI

72B3 29B4

BI

72B3 29B2

BI

72B3 29C2

BI

72B3 29B4

BI

72B3 29B2

BI

72B3 29B4

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C4

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29C2

BI

72B3 29C2

BI

72B3 29C4

BI

72B3 29D2

BI

72B3 29D2

BI

72B3 29C4

BI

72B3 29C2

BI

72B3 29D4

BI

72B3 29C4

BI

72A3 29A7

OUT

72A3 29B5

OUT

72B3 29B7

OUT

OUT

28C5 72D3

72B3 29B5

OUT

OUT

28C5 72D3

72B3 29B4

OUT

72B3 29C2

OUT

OUT

28D5 72D3

72B3 29C2

OUT

OUT

28D7 72D3

72B3 29C4

OUT

BA8 BC8 BB4 BC4 BA7 AY8 BA9

BB10 BB12 AW12 BB8 BB9

AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40

AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42

MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM

AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42

MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N

MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N

AT2 AT1 AY2 AY1 BB6 BA6 BA10

y r

a n i

28C7 72D3

TP_MEM_A_CLK2P TP_MEM_A_CLK2N

AW33


28C7 72D3

e r

MEMORY CONTROL 0A MCLK0A_2_P MCLK0A_2_N

OUT

BI

72B3 29B7

72B3 29B7

MBA0_2 MBA0_1 MBA0_0

BI

BI

72B3 29B7

MRAS0# MCAS0# MWE0#

BI

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ

MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0

MEMORY PARTITION 1

8

AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43

MRAS1# MCAS1# MWE1#

AW16

MBA1_2 MBA1_1 MBA1_0

BB29

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

BA29

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

BA15 BA16

BB17

AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18

29A5 72A3

BI

29B7 72A3

BI

29B7 72A3

BI

29B5 72A3

BI

29B5 72A3

BI

29B7 72A3

BI

29B7 72A3

BI

29B2 72A3

BI

29B2 72A3

BI

29C4 72A3

BI

29C4 72A3

BI

29C4 72A3

BI

29C4 72A3

BI

29C2 72A3

BI

29C2 72A3

29C5 72B3

OUT

29C7 72B3

OUT

29C7 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C7 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C5 72B3

OUT

29C7 72B3

OUT

29C5 72B3

MEM_B_CLK_P MEM_B_CLK_N

OUT

29C5 72B3

OUT

29C5 72B3


OUT

29C7 72B3

OUT

29C7 72B3

MEM_B_CS_L MEM_B_CS_L

OUT

29C7 72B3

OUT

29C5 72B3

MEM_B_ODT MEM_B_ODT

OUT

29C5 72B3

OUT

29C5 72B3

MEM_B_CKE MEM_B_CKE

OUT

29D5 72B3

OUT

29D7 72B3

MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A

BA14

29A5 72A3

BI

OUT

MEM_B_BA MEM_B_BA MEM_B_BA

BB18

BI

D

C

MEMORY CONTROL 1A MCLK1A_2_P MCLK1A_2_N

BA42


BB22


BA19

MCS1A_1# MCS1A_0#

BB14

MODT1A_1 MODT1A_0

BB13

MCKE1A_1 MCKE1A_0

AY31

TP_MEM_B_CLK2P TP_MEM_B_CLK2N

BB42

BA22

AY19

BB16

AY15

BB30

B

MCP Memory Interface SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 15

1

109

A

8

6

7

2

3

4

5

1

OMIT

U1400 MCP79-TOPO-B BGA

24C8 16C3 8B7

24B2

=PP1V8R1V5_S0_MCP_MEM


BB24


BA21

TP_MEM_A_CS_L TP_MEM_A_CS_L

AU17

TP_MEM_A_ODT TP_MEM_A_ODT

AN17

TP_MEM_A_CKE TP_MEM_A_CKE

AV23

AU34

BC24

BB21

AR15

AN15

AN25

MCLK0B_1_P MCLK0B_1_N MCLK0B_0_P MCLK0B_0_N MCS0B_0# MCS0B_1# MODT0B_0 MODT0B_1 MCKE0B_0 MCKE0B_1

17 12 19 39

R1610 1 40.2

72A3

mA mA mA mA

T27 U28 U27 T28

+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

AN41 AM41

40.2

AA22 AP12 2

G30 P10 T10 T6 V10 V34

AY23

MCLK1B_0_P MCLK1B_0_N

BA20

MCS1B_0# MCS1B_1#

BC16

MODT1B_0 MODT1B_1

AY16

MCKE1B_0 MCKE1B_1

BA30

MRESET0#

AY32

AA39 AB22 AB7

AD22 AE20 AF24 AG24 AH35 AK7

AM28 AT25 AP30 AR36

e r

B

P

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54

D


BA23

y r


AY20

TP_MEM_B_CS_L TP_MEM_B_CS_L

BA13

TP_MEM_B_ODT TP_MEM_B_ODT

BC13

TP_MEM_B_CKE TP_MEM_B_CKE

a n i

BA31

MCP_MEM_RESET_L

OUT

30B6

TP or NC for DDR2.

=PP1V8R1V5_S0_MCP_MEM +VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45

AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20

8B7 16C7 24C8

4771 mA (A01, DDR3)

C

m il W5

A



BB41

MEM_COMP_VDD MEM_COMP_GND

R1611 1 1% 1/16W MF-LF 402

BA41

2 72A3

C


PP1V05_S0_MCP_PLL_CORE

87 mA (A01)

1% 1/16W MF-LF 402


MEMORY CONTROL 1B

D

AU33

MEMORY CONTROL 0B

(4 OF 11)


AU10 F28

BC21 AY9 BC9 D34 F24 G32 H31 K7

M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20

AK11 T24 T26

GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64

AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29

B

AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31

T33 T34 T35 T37 T38 T7

MCP Memory Misc

T9 U18

SYNC_MASTER=T18_MLB

U20



U22


DRAWING NUMBER

D APPLE INC.

8

7

SCALE

SHT NONE


6

5

4

3

2

REV.

051-7537

A

OF 16

1

109

A

8

6

7

2

3

4

5

1

OMIT


IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

D

IN

9D6

IN IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6

IN

9D6 9D6

C

IN

9D6

9D6

9D6

=PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N =PEG_D2R_P =PEG_D2R_N

IN IN

31D7

IN IN

9D6

IN

9D6

IN

9C6

IN

9C6

IN

D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7 J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4

C9

PEB_CLKREQ#/GPIO_49

PEB_PRSNT# Int PU

FW_CLKREQ_L PCIE_FW_PRSNT_L

E8

PEC_CLKREQ#/GPIO_50

OUT

9C4

IN

TP_MCP_GPIO_18 GMUX_JTAG_TDO

31C7 23C5 7D5

IN

PCIE_WAKE_L

C10

73D3 31C7 7D5

IN

9D6

IN

9D6

IN

9C6

IN

B

9C6

PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_D2R_P PCIE_FW_D2R_N

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

IN

9B6

TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

8A6

=PP1V05_S0_MCP_PEX_DVDD0

9B6

P

A

57 mA (A01, DVDD0 & 1)

Int PU

PEC_PRSNT# Int PU PED_CLKREQ#/GPIO_51

B10

PED_PRSNT# Int PU

L16

PEE_CLKREQ#/GPIO_16

L18

PEE_PRSNT#/GPIO_46

M16

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

M17

Int PU

Int PU

Int PU

C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1

J2 J3 K2 K3 L4 L3 M4 M3 M2 M1

PE0_REFCLK_P PE0_REFCLK_N

E11


G11


J11

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

D

y r

D11

F11

J10

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

OUT

9D6

PEG_CLK100M_P PEG_CLK100M_N

OUT

9D6

OUT

9D6

PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N

OUT

31C5 73D3

OUT

31C5 73D3

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

OUT

9C6

OUT

9C6

PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N

OUT

9C6

OUT

9C6


G13


J13


L14


N14 M14

TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N

F13

H13

K14


9B6


F17

Int PU PE_WAKE# Int PU (S5)

PEX_RST0#

K11

PCIE_RESET_L

OUT

26C4

PE1_RX0_P PE1_RX0_N

PE1_TX0_P PE1_TX0_N

D8

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

OUT

31C5 73D3

OUT

31C5 73D3

PE1_RX1_P PE1_RX1_N

PE1_TX1_P PE1_TX1_N

B8

PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N

OUT

9D6

OUT

9D6

PE1_RX2_P PE1_RX2_N

PE1_TX2_P PE1_TX2_N

A7

PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N

OUT

9C6

OUT

9C6

PE1_RX3_P PE1_RX3_N

PE1_TX3_P PE1_TX3_N

B6

H9 G9 F9 E9 H7 G7

C8

A8

B7

C6

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

=PP1V05_S0_MCP_PEX_AVDD0

T17 W19 U17 V19 W16 W17 W18 U16

+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8

T19 U19

+DVDD1_PEX1 +DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13

Y12

+AVDD1_PEX1 +AVDD1_PEX2 +AVDD1_PEX3

M13

B

9B6 9B6

8A6

206 mA (A01, AVDD0 & 1)

AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12

=PP1V05_S0_MCP_PEX_AVDD1

8A6

N13

MCP PCIe Interfaces

P13

NO STUFF 1

SYNC_MASTER=T18_MLB

R1710

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

2.37K

2

C

9B6

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

J9

MCP_PEX_CLK_COMP

OUT

a n i

J1

Int PU

84 mA (A01) 73C3

D4

M19

K9

PP1V05_S0_MCP_PLL_PEX

24C2

=PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N =PEG_R2D_C_P =PEG_R2D_C_N

C5

Int PU

=PP1V05_S0_MCP_PEX_DVDD1

8A6

PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N

m il Int PU

M15

M18

e r IN

Int PU

D9

TP_MCP_GPIO_17 GMUX_JTAG_TCK_L

73D3 31C7 7D5

Int PU PE0_PRSNT_16#

D5

TP_PE4_CLKREQ_L TP_PE4_PRSNT_L

9C6

PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N

MINI_CLKREQ_L PCIE_MINI_PRSNT_L

EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L

9C6

9C4

E7

PEG_PRSNT_L

IN

31D7 9C6

F7

PCI EXPRESS

9D6

1% 1/16W MF-LF 402



PLACEMENT_NOTE=Place within 12.7mm of U1400


DRAWING NUMBER

D APPLE INC.

8

7

SCALE

SHT NONE


6

5

4

3

2

REV.

051-7537

A

OF 17

1

109

A

8

6

7

2

3

4

5

1

OMIT


24B6 24A6 18D3 8B1


75D3 33C1

IN

75D3 33C1

IN

75D3 33C1

IN

75D3 33B1

IN

75D3 33C1

IN

75D3 33B1

IN

9C4

IN

9C4

IN

9C4

ENET_RXD ENET_RXD ENET_RXD ENET_RXD

IN

B23 E24 A24

49.9

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

=MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS

F23

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

B26 B22 J22

5 mA (A01)

J24

+3.3V_DUAL_RMGT2

K24

+V_DUAL_RMGT1 +V_DUAL_RMGT2

U23

MII_VREF

E28

MCP_MII_VREF

RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

B24

ENET_TXD ENET_TXD ENET_TXD ENET_TXD

T23

MCP_MII_COMP_VDD 75D3 MCP_MII_COMP_GND

+V_DUAL_MACPLL

C27

MII_COMP_VDD MII_COMP_GND

B27

9D4

OUT

9D4

OUT

1

47K 5% 1/16W MF-LF 402 41C3

9D4

IN

9D4

OUT

E36 A35

Interface Mode MCP Signal

TMDS/HDMI

DisplayPort

=MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_TXD_P/N =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD DP_IG_AUX_CH_P/N

TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N TMDS_IG_TXD_P/N TMDS_IG_TXD_P/N TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N

DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_ML_P/N DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V

C38 D38

LPCPLUS_GPIO DP_IG_CA_DET

BI IN

70A7 69A8

OUT

70C8 70B7

OUT

66B8

OUT

67D3

OUT

67D3

OUT

67D3 67D3

OUT OUT

67D3

OUT

67D3

OUT

67D3

OUT

73B3 67C7

OUT

9B4

OUT

IN

P 67D3

IN

TV_DAC_RSET TV_DAC_VREF

DP_IG_AUX_CH_P DP_IG_AUX_CH_N

=DVI_HPD_GMUX_INT =MCP_HDMI_HPD

GPIO_6/FERR*/IGPU_GPIO_6

GPIO_7/NFERR*/IGPU_GPIO_7

G39

D35 E35 G35 F35 F33 G33 J33 H33

D43 C43

C31 F31

LCD_BKL_CTL/GPIO_57 LCD_BKL_ON/GPIO_59 LCD_PANEL_PWR/GPIO_58

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET2/GPIO_22 HPLUG_DET3


190 mA (A01, 1.8V)

M27 M26

PP3V3_S0_MCP_VPLL

16 mA (A01)

25D7 8B7

73B3 25C7

(See below)

XTALIN_TV XTALOUT_TV

B15

F40

=MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N

=PP1V05_S0_MCP_HDMI_VDD

95 mA (A01) MCP_HDMI_RSET OUT MCP_HDMI_VPROBE OUT

8 mA 8 mA

TV C Y Comp

E16

E37

=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N

25D7 8A7

73B3 25C7

(See below)

e r

OUT

67D3

73B3 67B7

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

25B5

33C8 75D3

OUT

33B6 75C3

OUT

33B6 75D3

C21 G23

TP_ENET_PWRDWN_L

BUF_25MHZ

E23

MCP_CLK25M_BUF0_R

MII_RESET#

J23

ENET_RESET_L

a n i

J32 K32

DDC_CLK0 DDC_DATA0

B31

RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE

B39

RGB_DAC_HSYNC RGB_DAC_VSYNC Component Pr TV_DAC_RED Y TV_DAC_GREEN Pb TV_DAC_BLUE

A40

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

D36

IFPA_TXC_P IFPA_TXC_N

B35

IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N

B32

IFPB_TXC_P IFPB_TXC_N

L31

IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

J29

DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24

C30

DDC_CLK3 DDC_DATA3

D31

IFPAB_RSET IFPAB_VPROBE

E32

/ / / /

103 mA 103 mA

M28 M29

+VDD_IFPA +VDD_IFPB +V_PLL_IFPAB +V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET HDMI_VPROBE

J30

BI

33B6 75D3

OUT

34A5 75D3

OUT

33B7 75C3

25D2

206 mA (A01)

MCP_DDC_CLK0 MCP_DDC_DATA0

A31

B40

Network Interface Select Interface

1

MII

0

=PP3V3_S0_MCP_GPIO

R1860 1

1

100K 5% 1/16W MF-LF 402

8C5 19D1 21A4

R1861 100K

2

2

5% 1/16W MF-LF 402

C

RGB DAC Disable: Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.

TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC

A41

CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB

A36 B36 C36

C37

C35

OUT

9D4

OUT

9D4

OUT

9D4

CRT_IG_HSYNC CRT_IG_VSYNC

OUT

9D4

OUT

9D4

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N

OUT

66B3 73B3

OUT

66B3 73B3

OUT

7C7 66C2 73B3

OUT

7C7 66C2 73B3

OUT

7C7 66C2 73B3

OUT

7C7 66C2 73B3

OUT

7C7 66C2 73B3

OUT

7C7 66C2 73B3

OUT

9D4

OUT

9D4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

OUT

9C4

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

OUT

7C7 66C5

=MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA

OUT

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

OUT

25C6 73A3

OUT

25C6 73A3

LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N

A32 D32 C32 D33 C33 B34 C34

TV DAC Disable: Okay to float all TV_DAC signals. Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N

K31

LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N

H29 L29 K29 L30 K30 N30 M30

B30

E31

G31

1

BI

BI

B

7C7 66B5

67D3 67D3

R1850 10K

In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.

2

5% 1/16W MF-LF 402

MCP Ethernet & Graphics SYNC_MASTER=T18_MLB



=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI. Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.


DRAWING NUMBER

D APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE


8

ENET_TXD

RGMII

NOTE: All Apple products set strap to MII, RGMII products will enable feature via software. This avoids a leakage issue since MCP79 requires a S5 pull-up.

TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE

A39

GPIOs 57-59 (if LCD panel is used):

A

OUT

RGMII_PWRDWN/GPIO_37

m il


2

67A5

B

MCP_TV_DAC_RSET MCP_TV_DAC_VREF

33C6 75C3

ENET_CLK125M_TXCLK ENET_TX_CTRL ENET_MDC ENET_MDIO

RGB ONLY

B38

33C6 75C3

OUT

33C6 75C3

D21

RGB_DAC_RSET RGB_DAC_VREF

OUT

33B6 75C3

RGMII_MDC RGMII_MDIO

FLAT PANEL

2

C39

DACS

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

y r

24A4

OUT

C26

+V_RGB_DAC +V_TV_DAC

IN

OUT

PP3V3_S0_MCP_DAC

=PP3V3_S5_MCP_GPIO

R1820

D25

1

C

20C1 8A3

C25

D24

49.9 1% 1/16W MF-LF 402

C24

RGMII_TXC/MII_TXCLK

2

D

8B1 24C6

131 mA (A01)

V23

RGMII_TXCTL/MII_TXEN

RGMII_INTR/GPIO_35

8B1 18C7 24A6 24B6

83 mA (A01) =PP1V05_ENET_MCP_RMGT

PP1V05_ENET_MCP_PLL_MAC

24A6

75D3

R1811

RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3

ENET_CLK125M_RXCLK ENET_RX_CTRL

TP_ENET_INTR_L

R1810 1 1% 1/16W MF-LF 402

C23

LAN

D

=PP3V3_ENET_MCP_RMGT +3.3V_DUAL_RMGT1

A

OF 18

1

109

A

8

6

7

2

3

4

5

1

OMIT

U1400

21A4 18C1 8C5

=PP3V3_S0_MCP_GPIO

MCP79-TOPO-B BGA (7 OF 11)

19D2 52C7

D

OUT OUT

19D2

IN

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

74D3 13C3

BI

C

41D5 39C5

9C4

41D3 39C8

IN

IN

BI

MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG MCP_DEBUG TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD TP_PCI_AD

T2 V9 T3 U9 T4

AC3 AE10 AC4 AE11 AB3 AC6 AB2 AC7 AC8 AA2 AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 T5 U7

PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

TP_PCI_INTW_L TP_PCI_INTX_L TP_PCI_INTY_L TP_PCI_INTZ_L

P2

N1

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

TP_PCI_TRDY_L

Y3

PCI_TRDY#

PM_CLKRUN_L

N3 N2

AD11

FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ

AE2 AE1 AE6

PCI_CLKRUN#/GPIO_42 LPC_DRQ1#/GPIO_19 Int PU Int PU LPC_DRQ0# LPC_SERIRQ Int PU

19D4

PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#

PCI

74D3 19D2

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

PCI_PME#/GPIO_30 Int PU (S5)

PCI_RESET0# PCI_RESET1#

PCI_CLK0 PCI_CLK1 PCI_CLK2

TP_PCI_GNT0_L TP_PCI_GNT1_L GMUX_JTAG_TMS GMUX_JTAG_TDI MCP_RS232_SOUT_L

R3 U10 R4 U11 P3

U39 U4 U8 V16

B

V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22

A

Y24 Y25

GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97

9C4

OUT

9C4

OUT

19D2

19D7 19D7

AA6 AA11 W10

Y2

TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L

T1

PM_LATRIGGER_L

OUT

13B6 23C5

R10

MEM_VTT_EN_R TP_PCI_RESET1_L

OUT

26C4

AA9 Y4 AA10 Y1 AB9 AA7

R11

R6 R7 R8

74C3

PCI_CLKIN

LPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI#

R9

AE5

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

AD3

GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130

AD2 AD1 AD5

AE9

Y26

41C1

P

H34

AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4

5% 1/16W MF-LF 402

LPC_FRAME_R_L LPC_PWRDWN_L

LPC_AD_R LPC_AD_R LPC_AD_R LPC_AD_R

1

2

8.2K 8.2K 8.2K 8.2K

1

2

1

2

1

2

1

2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

C

PLACEMENT_NOTE=Place close to pin R8

R1960

22

1

2

LPC_RESET_L

R1950 R1951 R1952 R1953

22 22 22 22

1

2

1

2

1

2

1

2

LPC_CLK33M_SMC_R

LPC_FRAME_L

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

LPC_AD LPC_AD LPC_AD LPC_AD

OUT

39C8 41D5 74C3

OUT

39C5 41D3

OUT

26D4 74C3

BI

39C8 41D5 74C3

BI

39C8 41D5 74C3

BI

39C8 41D3 74C3

BI

402

OUT

39C8 41D3 74C3

26C4 74C3

R1961 10K

e r Y27

AB18

PCI_CLK33M_MCP

8.2K

R1990 R1991 R1992 R1994

a n i

R1910

m il

AD4 AE12

LPC_RESET0#

LPC_CLK0

74C3

R1989

PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L MCP_RS232_SIN_L

y r

TP_PCI_CLK0 TP_PCI_CLK1 PCI_CLK33M_MCP_R

2

MCP_RS232_SOUT_L

D

22

GND

U26

74D3 19D7

OUT

TP_PCI_C_BE_L TP_PCI_C_BE_L TP_PCI_C_BE_L TP_PCI_C_BE_L

AA3

1

U24

74D3 19D7

1

LPC

74D3 19D2

2

5% 1/16W MF-LF 402

Strap for Boot ROM Selection (See HDA_SDOUT)

B

AB40 AC22 AC36 AC40 AB33 AC5

AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27

MCP PCI & LPC

AD28 AD33

SYNC_MASTER=T18_MLB


AD34


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 19

1

109

A

8

6

7

2

3

4

5

1

OMIT

U1400 MCP79-TOPO-B BGA (8 OF 11) 73A3 36A3 73A3 36A3

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

OUT OUT

73A3 36A3

IN

73A3 36A3

IN

AJ7

SATA_HDD_D2R_N SATA_HDD_D2R_P

AJ6

AJ5 AJ4

SATA_A0_TX_P SATA_A0_TX_N

USB0_P USB0_N

SATA_A0_RX_N SATA_A0_RX_P

USB1_P USB1_N

D

USB2_P USB2_N OUT

73A3 36C2

OUT

73A3 36B2 73A3 36B2

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

AJ11 AJ10

SATA_ODD_D2R_N SATA_ODD_D2R_P

IN IN

AJ9 AK9

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

AK2

TP_SATA_C_D2RN TP_SATA_C_D2RP

AJ3

AJ2 AJ1

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

AM4

TP_SATA_D_D2RN TP_SATA_D_D2RP

AL3

AL4 AK3

TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN

C

AN1

TP_SATA_E_D2RN TP_SATA_E_D2RP

AM1

AM2 AM3

TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN

AP3

SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P

SATA_B1_TX_P SATA_B1_TX_N SATA_B1_RX_N SATA_B1_RX_P

SATA_C0_TX_P SATA_C0_TX_N

AP2

AN3 AN2

TP_MCP_SATALED_L

PP1V05_S0_MCP_PLL_SATA

84 mA (A01) 8A6 =PP1V05_S0_MCP_SATA_DVDD0

e r =PP1V05_S0_MCP_SATA_DVDD1

8A6

B

=PP1V05_S0_MCP_SATA_AVDD0

8A6

127 mA (A01, AVDD0 & 1)

P 8A6

73A3

1

B28

F29

SATA_C1_TX_P SATA_C1_TX_N SATA_C1_RX_N SATA_C1_RX_P

E12

AE16

AF19 AG16 AG17 AG19

AH17 AH19

AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13

SATA_LED#

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4 +DVDD1_SATA1 +DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

AN14 AL14 AM13 AM14

AE3

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4 SATA_TERMP

BI

37A8 74C3

BI

37A8 74C3

AirPort (PCIe Mini-Card) USB_MINI_P USB_MINI_N

BI

9B6

BI

9B6

External D USB_EXTD_P USB_EXTD_N

BI

9B6

BI

9B6

USB_CAMERA_P USB_CAMERA_N

BI

31B5 74C3

BI

USB4_P USB4_N

K27

31B5 74C3

USB_IR_P USB_IR_N

BI

38C7 74B3

BI

USB5_P USB5_N

J26

38C7 74B3

Geyser Trackpad/Keyboard USB_TPAD_P USB_TPAD_N

BI

47B8 74B3

BI

USB6_P USB6_N

F27

47B8 74B3

Bluetooth USB_BT_P USB_BT_N

BI

31B5 74B3

BI

31B5 74B3

External B USB_EXTB_P USB_EXTB_N

BI

37A4 74B3

BI

37A4 74B3

ExpressCard USB_EXCARD_P USB_EXCARD_N

BI

9B6

BI

9B6

External C USB_EXTC_P USB_EXTC_N

BI

9B6

BI

9B6

G29

USB7_P USB7_N USB8_P USB8_N USB9_P USB9_N

L27

J27

G27

D

y r

a n i

D27 E27

K25 L25

H25 J25

USB10_P USB10_N

F25

USB11_P USB11_N

K23

USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

L21

+V_PLL_USB

L28

G25

L23

SATA_C0_RX_N SATA_C0_RX_P

=PP1V05_S0_MCP_SATA_AVDD1

MCP_SATA_TERMP

A28

USB3_P USB3_N

USB_RBIAS_GND

43 mA (A01, DVDD0 & 1)

D28

K21 J21 H21

m il

TP_SATA_F_D2RN TP_SATA_F_D2RP

24B2

C28

External A USB_EXTA_P USB_EXTA_N

IR

SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P

D29

Camera

SATA USB

73A3 36C2

C29

GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160

A27

AD35 AD37 AD38

TP_USB_10P TP_USB_10N

R2050

TP_USB_11P TP_USB_11N

PP3V3_S0_MCP_PLL_USB

=PP3V3_S5_MCP_GPIO

1

1

R2051 8.2K

2

1

R2053 8.2K

5% 1/16W MF-LF 402

2

R2052

8.2K

8.2K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

8A3 18C7

5% 1/16W MF-LF 402

C

1

2

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L

IN

37C7

IN

37C7

IN IN

40B4

24B4

19 mA (A01)

74B3

MCP_USB_RBIAS_GND

R2060 1 806

1% 1/16W MF-LF 402

2

AE22 AE24 AE39 AE4 AD6

AF16 AF17 AF18

B

AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24

R2010 2.49K

2

A

1% 1/16W MF-LF 402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

MCP SATA & USB SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

8

7

SCALE

SHT NONE


6

5

4

3

2

REV.

051-7537

A

OF 20

1

109

A

8

6

7

2

3

4

5

1

OMIT

U1400

=PP3V3R1V5_S0_MCP_HDA

MCP79-TOPO-B

8B5 21D8 24A8

7 mA (A01)

BGA (9 OF 11)

HDA

+V_DUAL_HDA1 +V_DUAL_HDA2

D 74A3 51C7

HDA_SDIN0

IN

G15

TP_MLB_RAM_SIZE

24A8 21D3 8B5

J14

TP_MLB_RAM_VENDOR


J15

(MXM_OK for MXM systems) 1

HDA_SDATA_IN0 Int PD

HDA_SDATA_OUT

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK Int PD

HDA_BITCLK

41B1

1% 1/16W MF-LF 402

OUT IN

R2121 49.9K

2

2

HDA_SDOUT_R

22

1

74B3 21A7

22

HDA_BIT_CLK_R

1

HDA_RESET#

K15

74A3 21A7

L15

74A3 21A7

22

22

2

HDA_RST_L

5% 1/16W MF-LF 402

HDA_SYNC

2

MCP_HDA_PULLDN_COMP

A15

1% 1/16W MF-LF 402

39C5 23C5

IN

39B8 23C5

IN

HDA_PULLDN_COMP

HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA

K17

SLP_S3# SLP_RMGT# SLP_S5#

G17

THERM_DIODE_P THERM_DIODE_N

B11

a n i

MCP_GPIO_4 AUD_I2C_INT_L

L17

PP1V05_S0_MCP_PLL_NV 20 mA 17 mA

=SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN

AE18 AE17

+V_PLL_NV_H +V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12/SUS_STAT#/ACCLMTR

TP_SB_A20GATE TP_MCP_KBDRSTIN_L SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L

K13

C18

Int PU A20GATE KBRDRSTIN# Int PU SIO_PME# Int PU (S5) EXT_SMI/GPIO_32# Int PU (S5)

SM_INTRUDER_L

B20

INTRUDER#

L13 C19

21A4

IN

PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L

J17 H17

MCP_THMDIODE_P MCP_THMDIODE_N

C11

21A4 52C7

OUT

7C3 34B7 39C5 41A5 64D5 68D8

OUT

9D1

OUT

7C3 39C5 40A2 64C8

OUT

45C5 77D3

OUT

45B5 77D3

OUT

21A3 61A8

OUT

21A3 61A8

OUT

21A3 61A8

IN

71B3 60D8

IN

PM_DPRSLPVR

M22

CPU_DPRSLPVR

39C8 23C5

IN

C16

26A1 23C5

IN

PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L

D16

PWRBTN# Int PU (S5) RSTBTN# Int PU

RTC_RST_L

C20

RTC_RST#

MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15

L20

M21

MCP_VID MCP_VID MCP_VID

SPKR

C13

MCP_SPKR

SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT#/GPIO_64

L19

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN

FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62

B12

C12

MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT

CPUVDD_EN

D17

MCP_CPUVDD_EN

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9

C14

SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R

M20

1

26A5

IN

E20

IN

MCP_CPU_VLD

C17

CPU_VLD

JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK

E19

JTAG_TDI Int PU JTAG_TDO JTAG_TMS Int PU JTAG_TRST# JTAG_TCK

IN

IN OUT

23C5 13C3 6C5

IN

13C3 6C5

IN

13B6 6C5

IN

B 26B7 26C7

26C7 26C7

IN OUT

IN OUT

J19 J18 G19


A16 B16

RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT

A19 B19

1

10K

HDA_RST_R_L HDA_SYNC_R

A

C2170

C2172

1

10PF

10PF

5% 50V CERM 402

5% 50V CERM 402

2

1

2

C2171

21D4 74B3

21D4 74A3 21C4 74A3

1

2

XTALIN XTALOUT

XTALIN_RTC XTALOUT_RTC

100K

2

2

5% 1/16W MF-LF 402

1

2

R2140

1

R2141

1

SUS_CLK/GPIO_34 BUF_SIO_CLK TEST_MODE_EN PKG_TEST

10PF

5% 50V CERM 402

5% 50V CERM 402

2

F21 M23

A12 D12

D13 C15 B14

OUT

BI

OUT

BI

OUT

IN

OUT

51C7 74A3

LPC_FRAME#

0

0

PCI

0

1

SPI0

1

0

SPI1

1

1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override. NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

8C5 22B3 24B8

IN

=PP3V3_S0_MCP_GPIO

13B6 42D8 74B3

Frequency 23B5

2

42C8 74B3

R2142

OUT

10K

10K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L ARB_DETECT

2

1

14.31818 MHz

0

USER mode: Normal SAFE mode: For ROMSIP recovery

SPI Frequency Select

Connects to SMC for automatic recovery.

Frequency

SPI_DO

SPI_CLK

0

0

42 MHz

0

1

25 MHz

1

0

1 MHz

1

1

21A4 28A5 29A5 39B8 36C6

31 MHz

21A4 40D4

26A8

OUT

41B7 74A3

OUT

41A5 41C8 74A3

IN

41A5 41B7 74A3

OUT

41A5 41C7 74A3

OUT

26B4 74A3

NOTE: Straps not provided on this page.

B

L22

1

R2163

R2190 1K

5% 1/16W MF-LF 402

2

1% 1/16W MF-LF 402

8C5 18C1 19D1

2

8D3

R2154 100K

1

5% 1/16W MF-LF 402

AP_PWR_EN

21C3

21B3 31D5 34C7

21C3 52C7

MCP HDA & MISC

21B3 28A5 29A5 39B8


21B3 40D4

21B3

1

R2147

R2155

1

R2156

100K

22K

22K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

2

1

21C3 61A8

SYNC_MASTER=T18_MLB


21C3 61A8


R2157 22K

2


21C3 61A8


5% 1/16W MF-LF 402


DRAWING NUMBER

D APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE


8

HDA_SYNC

24 MHz

MCP_TEST_MODE_EN

K22

R2143

10K

5% 1/16W MF-LF 402

21A3 31D5 34C7

=PP3V3_S3_MCP_GPIO 1

R2181 10K

13B6 42D8 74B3

42C8 74B3

C

BUF_SIO_CLK Frequency

5% 1/16W MF-LF 402

21A4

PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK

B18

AE7

2

C2173

10PF

G21

10K

5% 1/16W MF-LF 402

2

K19

1

1

1

(MGPIO2)

10K

2

OUT

HDA_SDOUT

LPC

10K

OUT

m il

R2151

P 5% 1/16W MF-LF 402

51B7 74A3

I/F

BOOT_MODE_USER

e r F19

R2150 1

21D4 74A3

D20

R2180

1

(MGPIO3)

26A5

6C4

HDA_SDOUT_R HDA_BIT_CLK_R

LID# Int PU (S5) LLB# Int PU (S5)

PWRGD_SB PS_PWRGD

23C5 13C3 6C5

For EMI Reduction on HDA interface

M24

PM_RSMRST_L MCP_PS_PWRGD

39C8

HDA Output Caps

M25

OUT

BIOS Boot Select

BOOT_MODE_SAFE

MISC

39B8 23B5

TP_MCP_LID_L PM_BATLOW_L

51C7 74B3

=PP3V3_S0_MCP

2

23C5

51C7 74A3

y r OUT

R2172 1

1

OUT

HDA_BIT_CLK

2

HDA_RST_R_L

HDA_SYNC_R

HDA_SDOUT

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA Int PD

2

5% 1/16W MF-LF 402

40B2 39D5 34B7

49.9K

E15

D

R2170

74A3 21A7

R2173

PP3V3_G3_RTC

C

5% 1/16W MF-LF 402

R2171

HDA_SYNC

37 mA (A01)

1

8.2K

1% 1/16W MF-LF 402

24A2

R2120 1

F15

R2160

R2110

74A3

26D4 22A5 7C3

1

K16

2

49.9

2

J16

A

OF 21

1

109

A

8

6

7 OMIT

U1400

MCP79-TOPO-B

MCP79-TOPO-B

AH37 AH38 AJ39

D

AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9

C

AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33

B

AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43

A

AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41

GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343

61B1 44D7 24D8 8C8

AV40

BGA (10 OF 11)

=PPVCORE_S0_MCP AA25

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

BA1

AC23

BA4

U25

AW31

AH12

AY6

AG10

L35

AG5

BC33

Y21

BC37

Y23

BC41

AA16

AY14

AA26

BC5

AA27

C2

AA28

D10

AC16

D14

AC17

D15

AC18

D18

AC19

D19

AC20

D22

AC21

D23

AA17

D26

AC24

D30

AC25

D37

AC26

D6

AC27

E13

AC28

E17

AD21

E21

AD23

E25

W27

E29

V25

E33

AA18

F12

AE19

F16

AE21

F32

AE23

F8

AE25

G10

AE26

G12

AE27

G14

AE28

G16

AF10

BC12

AF11

G22

AA19

G24

AF2

AW20

AF21

AF25

G4 G43

AF3

G6

AF4

G8

AF7

H11

AH23

H15

AF9

AW35

AA20

H23

AG11

AN8

AG12

G40

AG21

J12

AG23

J8

AG25

e r

K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10

P

M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11

=PP1V05_S0_MCP_FSB +VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52

R32

1139 mA

AG3 AG4

AA21 AG6 AG7 AG8 AG9 AH1

AH10 AH11 W26 AH2

AA23 W28

AH25 AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 W25 AF12

26D4 21C8 7C3

PP3V3_G3_RTC 10 uA (G3) 80 uA (S0)

A20

+VBAT

8D7 9C2 14A2 14B7 24C8

1182 mA (A01)

AC32 E40 J36 N32 T32

D

U32 V32

y r

W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41

a n i

B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34

m il AF23

G34

K10

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

POWER

AH34

GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252

GND

BGA (11 OF 11)

AH33

1

OMIT

U1400

AH26

2

3

4

5

K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32

C

AA32

+VTT_CPUCLK

AG32

+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8

AD10

43 mA

=PP3V3_S0_MCP

8C5 21C2 24B8

450 mA (A01)

B

AE8

AB10 AD9 Y10

AB11 AA8 Y9

=PP3V3_S5_MCP +3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

G18

+3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4

G26

+VDD_AUXC1 +VDD_AUXC2 +VDD_AUXC3

T21

16 mA

8A3 24B8

266 mA (A01)

H19 J20 K20

250 mA

H27 J28 K28

=PP1V05_S5_MCP_VDD_AUXC

8B3 24C8

105 mA (A01)

MCP Power & Ground

U21 V21

SYNC_MASTER=T18_MLB



Y11 AH16


T22


DRAWING NUMBER

D APPLE INC.

8

7

SCALE

SHT NONE


6

5

4

3

2

REV.

051-7537

A

OF 22

1

109

A

8

7

6

2

3

4

5

1

D

D

y r

3.3V Interface Pull-ups

a n i

These internal pull-ups are missing in Revs A01 & A01P. 41B4 8A3

OUT

PM_LATRIGGER_L

31C7 17B6 7D5

OUT

PCIE_WAKE_L

R2401

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2

21B7 13C3 6C5

OUT

JTAG_MCP_TDI

R2402


21B7 13C3 6C5

OUT

JTAG_MCP_TMS

R2403


OUT

PM_SYSRST_DEBOUNCE_L

OUT

TP_MCP_LID_L MCP_LID_L

19C4 13B6

C

=PP3V3_S5_MCP_A01

MCP_A01&MCP_A01P&MCP_A01Q 10K R2400 1 2

26A1 21B7

21C7

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

R2404 R2405

MAKE_BASE=TRUE

MF-LF

402

5%

1/16W

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2 MCP_A01&MCP_A01P&MCP_A01Q 10K 1 2

39C5 21C7

OUT

SMC_WAKE_SCI_L

MCP_A01&MCP_A01P&MCP_A01Q 10K R2410 1 2

39B8 21C7

OUT

SMC_RUNTIME_SCI_L

R2411

39C8 21B7

OUT

PM_PWRBTN_L

R2412


39B8 21C7

OUT

PM_BATLOW_L

R2413


5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402


m il 5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

C

MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE RADAR 5925345

e r

B

21C3

P

A

MCP_SPKR

R2430 1

0

2

SMC_MCP_SAFE_MODE

IN

B

39B5

5% 1/16W MF-LF 402

MCP79 A01 Silicon Support SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 24

1

109

A

8 MCP Core Power

2

3

4

5

1

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

=PPVCORE_S0_MCP

61B1 44D7 22D5 8C8

6

7

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V) (No IG vs. EG data)

D

C2500

1

C2501

1

C2502

1

C2503

4.7UF

4.7UF

4.7UF

4.7UF

20% 4V X5R 402

20% 4V X5R 402

20% 4V X5R 402

20% 4V X5R 402

2

2

2

1

1

2

1

C2504

2

1

C2506

1

C2507

1

C2508

C2509

1

1

C2510

1

C2511

C2512

1UF

1UF

1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

10% 10V X5R 402-1

10% 10V X5R 402-1

10% 10V X5R 402-1

10% 10V X5R 402-1

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

2

MCP PCIE (DVDD) Power

2

2

2

2

2

2

2

1

C2513 0.1UF

2

20% 10V CERM 402

MCP SATA (DVDD) Power

=PP1V05_S0_MCP_PEX_DVDD

8B7 8A8

1

C2505

1UF

57 mA (A01)

8B7

43 mA (A01)

30-OHM-5A

=PP1V05_S0_MCP_AVDD_UF 333 mA (A01)

1

y r

2 0603

C2515

1

1

2

2

4.7UF 20% 4V X5R 402

1

C2516 1UF

1

C2517 1UF

10% 10V X5R 402-1

2

1

C2518

C2519

0.1uF

10% 10V X5R 402-1

2

C2520

0.1uF

20% 10V CERM 402

20% 4V X5R 402

MCP 1.05V AUX Power

2

2

1

C2521 0.1uF

18D3 8B1

105 mA (A01)

C2570

2

20% 6.3V CERM 402-LF

a n i 1

2

0603

1

C2525

C2526

0.1uF 2

MCP FSB (VTT) Power 14B7 14A2 9C2 8D7 22D3

C2528

0.1uF

20% 10V CERM 402

1

2

2

20% 4V X5R 402

1

C2529

4.7uF

20% 10V CERM 402

2

1

0.1uF

2

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)

=PP1V05_S0_MCP_FSB

1

2

1

1

C2531

C2532

1

1

C2533

1

C2534

C2535

1

C2536

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

2

2

2

2

2

2

20% 4V X5R 402

C2540

1

1

4.7UF 20% 4V X5R 402

=PP3V3_S0_MCP

2

2

1

C2541

1

C2542

1

C2543

1

C2544 0.1UF

0.1UF

0.1UF

0.1UF

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

2

2

2

2

m il

C2550

1

C2551

1

C2552

1

2.2UF

2.2UF

2.2UF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

2

2

2

2

P

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

7 mA (A01) 1

C2562 2.2UF

2

20% 6.3V CERM 402-LF

A

L2595 30-OHM-1.7A

=PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)


83 mA (A01)

C2560 20% 6.3V CERM 402-LF

1

PP1V05_ENET_MCP_PLL_MAC MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

2 0402

C2595

1

1

4.7UF 20% 4V X5R 402

0.1UF

20% 10V CERM 402

20% 10V CERM 402

2

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_S0_MCP_PLL_USB 20C3 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

2

0402

1

1

2

2

C2573

C2574

2.2UF

20% 6.3V CERM 402-LF

2

2.2UF

20% 6.3V CERM 402-LF

2

20% 6.3V CERM 402-LF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

127 mA (A01)

C2576 2.2UF

2

20% 6.3V CERM 402-LF

14A6

270 mA (A01)

C

C2581 20% 10V CERM 402

2

C2582

1

20% 4V X5R 402

2

2

17A6

84 mA (A01)

C2583 0.1UF 20% 10V CERM 402

L2584

PP1V05_S0_MCP_PLL_SATA MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

2 0402

C2584

C2555

1

1

2

2

4.7UF 20% 4V X5R 402

20% 6.3V CERM 402-LF

20B6

84 mA (A01)

C2585 0.1UF 20% 10V CERM 402

B L2586 30-OHM-1.7A 1

PP1V05_S0_MCP_PLL_CORE

C2564

C2586

1

1

2

2

4.7UF

20% 6.3V CERM 402-LF

20% 4V X5R 402

16C6


2 0402

87 mA (A01)

C2587 0.1UF 20% 10V CERM 402

L2588 30-OHM-1.7A 1

PP1V05_S0_MCP_PLL_NV

C2588

1

1

4.7UF 20% 4V X5R 402

C2589

1

0.1UF 2

2

20% 10V CERM 402

37 mA (A01)

C2590 0.1UF

2

20% 10V CERM 402


R2591 1

MCP Standard Decoupling

1.47K 1% 1/16W MF-LF 402

SYNC_MASTER=T18_MLB 2

MCP_MII_VREF

OUT

18D3


5 mA (A01)

R2590 1

1

1.47K 1% 1/16W MF-LF 402 2

20% 10V CERM 402



18C6

C2596

21C7


2 0402

MCP79 Ethernet VRef

24B6 18D3 18C7 8B1

1

30-OHM-1.7A 1

2.2UF

2

1

4.7UF

19 mA (A01)


PP1V05_S0_MCP_PLL_PEX


2

0402

C2591


0.1UF 2


20% 10V CERM 402


DRAWING NUMBER

D APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE


8

206 mA (A01)

0.1UF

30-OHM-1.7A

1

2.2UF

0.1UF 2

2

MCP 3.3V Ethernet Power

24A6 18D3 18C7 8B1

2.2UF

8B1

1

C2549

0.1UF

30-OHM-1.7A

=PP3V3_S0_MCP_PLL_UF

e r

C2553

2.2UF


1


2

19 mA (A01)

266 mA (A01)

21D8 21D3 8B5

2

1

C2548

L2555

B

MCP 3.3V/1.5V HDA Power

2

1

C2547

0.1UF

20% 10V CERM 402

8B5

2

=PP3V3_S5_MCP

1

C2546

0.1UF

20% 10V CERM 402


1

22B3 8A3

1

C2545

0.1UF

450 mA (A01)

MCP 3.3V AUX/USB Power

C2572

1

L2582

=PP1V8R1V5_S0_MCP_MEM

MCP 3.3V Power

1

4.7UF

4771 mA (A01, DDR3)

22B3 21C2 8C5

1

2.2UF

2

PP1V05_S0_MCP_PLL_FSB

C2580

MCP Memory Power 16C7 16C3 8B7

20% 6.3V CERM 402-LF


2

0402

C2530

20% 6.3V CERM 402-LF

30-OHM-1.7A

=PP1V05_S0_MCP_PLL_UF 562 mA (A01)

1

C2575

L2580

8B7

1182 mA (A01)

C

2.2UF

2

2.2UF

20% 10V CERM 402

C2571

1

8A8


NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP1V05_S0_MCP_SATA_AVDD 8A8

L2575 30-OHM-5A

=PP1V05_ENET_MCP_RMGT 131 mA (A01)

1

1

2.2UF

20% 10V CERM 402

MCP 1.05V RMGT Power

=PP1V05_S5_MCP_VDD_AUXC

22A3 8B3

1

4.7UF

20% 10V CERM 402

2

1

D

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF) PP1V05_S0_MCP_PEX_AVDD

L2570

=PP1V05_S0_MCP_SATA_DVDD

8B7 8A8

A

OF 25

1

109

A

8

6

7

5

2

3

4

1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) 18B6 8A7

NO STUFF 8C5

190 mA (A01, 1.8V)

30-OHM-1.7A

=PP3V3_S0_MCP_DAC_UF 206 mA (A01)

1

1

C2610

D

18A6 8B7


2 0402

2.2UF 2

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP3V3_S0_MCP_DAC

L2650


NO STUFF 1

20% 6.3V CERM 402-LF

C2650

0 5% 1/16W MF-LF

20% 6.3V CERM 402-LF

y r

=PP1V05_S0_MCP_HDMI_VDD

1

1

2

2

4.7UF 20% 4V X5R 402

73B3 18A6

C

0.1UF

73A3 18A3

C2620 20% 10V CERM 402

2

1% 1/16W MF-LF 402

2

20% 10V CERM 402

=PP3V3_S0_MCP_VPLL_UF

1


2

C2640

1

1

2

2

4.7UF 20% 6.3V CERM 603

=PP3V3_S0_HDCPROM

20% 10V CERM 402

10K

NOSTUFF

5% 1/16W MF-LF 402

VCC U2695

2

AT24C08

A0 A1 3 A2

SOIC

1 2

SDA SCL

5

WP

7

4

4

A

NOSTUFF

VCC

U2690 AT24C01B SOT23

HDCPROM_WP

5

SDA SCL

WP

=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL

6

GND

25A7

P R2690 1

8

3

25A8

2

2

42C6

BI

IN

42C6

HDCPROM_WP

m il

16 mA (A01)

C2641 20% 10V CERM 402

B

MCP Graphics Support SYNC_MASTER=T18_MLB

2


SYNC FROM T18 REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC


7

DRAWING NUMBER

D APPLE INC.

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE


8



1

GND

C

e r

HDCP ROM WF: Open question on which packge option(s) nVidia can support.

1

2

1% 1/16W MF-LF 402

0.1uF

B

0.1UF

R2630 1K

0.1UF

0402

C2690

1

1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) L2640 Apple: ??? 30-OHM-1.7A PP3V3_S0_MCP_VPLL 18A6

16 mA (A01)

8B5

NO STUFF

NO STUFF

C2630

1K

0.1UF


R2620

1

a n i

20% 10V CERM 402

73A3 18A3

1

NO STUFF

8C5

C2616

MCP_HDMI_RSET MCP_HDMI_VPROBE

73B3 18A6

D

2 402

95 mA (A01)

C2615

206 mA (A01)

R2651

2.2UF 2

18C3

1

A

OF 26

1

109

A

8

6

7

2

3

4

5

1

1

RTC Power Sources Platform Reset Connections

VIN

U2801 MIC5232-2.8YD5

LPC Reset (Unbuffered)

TSOT-23-5 3

VOUT

5

NC

4

PP3V3_G3_RTC

D

1

C2870

R2819

2

2

10% 10V X5R 402

10% 10V X5R 402

C2819

2

C2871 0.47UF

GND

1UF 2

1

10%

100

1UF 6.3V

402

CERM 402

7C3 21C8 22A5

R2881

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

=PP3V42_G3H_RTC_D

1 MF-LF

8D1

EN

74C3 19B3

1

PLACEMENT_NOTE=Place close to U1400

LPC_RESET_L

IN

2

0.08F

RTC Crystal IN

1

1

R2810

PLACE C2819 CLOSE TO MCP79 PLACE C2800 AT COOLEST SPOT ON MLB

0

1

CRITICAL

10M

Y2810

5% 1/16W MF-LF 402 2 21B7

C

OUT

4

R2811

32.768K 1

C2811 12pF

7X1.5X1.4-SM

1

RTC_CLK32K_XTALIN

2

SMC_LRESET_L

OUT

39C8

BKLT_PLT_RST_L

OUT

70C8

MINI_RESET_L

OUT

31A6

PCA9557D_RESET_L

OUT

27A5

FC_RESET_L

OUT

32B3

D

5% 1/16W MF-LF 402

PCIE Reset (Unbuffered)

a n i

RTC_CLK32K_XTALOUT_R

NO STUFF

41D5

R2892

17B3

2 5% 50V CERM 402

5% 1/16W MF-LF 402 2

OUT

y r

PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

C2810

RTC_CLK32K_XTALOUT

33


12pF 21B7

DEBUG_RESET_L

R2883 1

C2800

2% 2 3.3V XHHG SM

2

5% 1/16W MF-LF 402

PP3V3_G3_SUPERCAP 1

33

1

2 5% 50V CERM 402

PCIE_RESET_L

IN

0

1

R2891 0

1

2

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

R2871 0

1

2

5% 1/16W MF-LF 402

R2872 0

1

2

5% 1/16W MF-LF 402

C

R2870

19C4

C2815

m il

12pF IN

1

MCP_CLK25M_XTALOUT

R28151 5% 1/16W MF-LF 402 2

R2816 1

MCP_CLK25M_XTALOUT_R

Y2815

4

25.0000M

2

CRITICAL

SM-3.2X2.5MM

OUT

NC NC

C2816

1

5% 1/16W MF-LF 402 2

3

1M

21B7

2 5% 50V CERM 402

0

NO STUFF

12pF 1

MCP_CLK25M_XTALIN

2

e r 5% 50V CERM 402

MCP S0 PWRGD & CPU_VLD

B

8A3

=PP3V3_S5_MCPPWRGD MCPSEQ_SMC 1

C2850 0.1UF

2

20% 10V CERM 402

P MCPSEQ_SMC

5 TC7SZ08AFEAPE 64A4 39D8

IN

60C7

IN

ALL_SYS_PWRGD VR_PWRGOOD_DELAY

2

1

SOT665

A

U2850Y B

3

4

R2853

S0_AND_IMVP_PGOOD

1

0

2

5% 1/16W MF-LF 402

MCPSEQ_MIX

R2852 0

1

MCPSEQ_MIX

R2851

1

0

5% 1/16W MF-LF 402

A

21B3

IN

MCP_CPUVDD_EN

2

5% 1/16W MF-LF 402

2

MCP_PS_PWRGD

MCP_CPU_VLD

33

MEM_VTT_EN_R

1

MEM_VTT_EN MAKE_BASE=TRUE

2

=DDRVTT_EN

OUT

OUT

74C3 19B3

74A3 21B3

IN

LPC_CLK33M_SMC

OUT

39C8 74C3

LPC_CLK33M_LPCPLUS

OUT

41D3 74C3

IN

PM_CLK32K_SUSCLK

OUT

39C5 74A3

R2825


LPC_CLK33M_SMC_R

33 1

2 5% 1/16W MF-LF 402

R2826 33 1


2 5% 1/16W MF-LF 402

R2829

PM_CLK32K_SUSCLK_R

1 PLACEMENT_NOTE=Place close to U1400

22

2

5% 1/16W MF-LF 402

B

Reset Button 39B8

IN

PM_SYSRST_L XDP

R2898

21B7

13B3 10C6

IN

XDP_DBRESET_L

1

0 5% 1/16W MF-LF 402

R2899

2

1

R28901

NO STUFF

0 5% 1/16W MF-LF 402 2

33 5% 1/16W MF-LF 402

SILK_PART=SYS RST

10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L

2

0

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

10% 10V X5R 402

21B7

SB Misc SYNC_MASTER=RAYMOND

SYNC FROM T18 CHANGE RESET BUTTOM TO RESET PADS REMOVE UNUSED PCIE RESET SIGNALS REMOVE R2824 AND NET PCI_CLK33M_SLOT_A CHANGE RTC COIN CELL TO LDO & SUPERCAP ALIAS MEM_VTT_EN TO =DDRVTT_EN CHANGE Y2810 AND U2850 TO SMALLER PARTS



DRAWING NUMBER

D APPLE INC.

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

6

21B7 23C5

C2899 1UF

2

2

5% 1/16W MF-LF 402

OUT

NO STUFF 1

R2850

1

7

59C8 65A3

MCPSEQ_SMC


8

OUT

5% 1/16W MF-LF 402

MCP 25MHz Crystal 21B7

IN

A

OF 28

1

109

A

8

6

7

2

3

4

5

1

Page Notes MEM A VREF DQ

Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PP3V3_S5_VREFMRGN - =PPVTT_S3_DDR_BUF

DAC channel Min DAC code Max DAC code Max sink I Max source I Nominal Vref Min Vref Max Vref Vref Stepping (per DAC LSB)

Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA

D

BOM options provided by this page: VREFMRGN NO_VREFMRGN

MEM A VREF CA

A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

MEM B VREF DQ

MEM B VREF CA

A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV

CPU FSB VREF C 0x00 0x55 -0.91 mA 0.52 mA 0.70 V 0.091 V 1.044 V 11.2 mV

SO-DIMM A and SO-DIMM B Vref settings should be margined separately (i.e. not simultaneously) due to current limitation of TPS51116 regulator. =PPVTT_S3_DDR_BUF 59D7 8C4

D

10mA max load

y r R2903 1

A2

V+

UCSP A1 VREFMRGN

0.1UF

20% 10V 2 CERM 402

=PP3V3_S3_VREFMRGN 8D3

A3

VREFMRGN

R2901

C2901

C2

V+

=I2C_VREFDACS_SCL

6 SCL

BI

=I2C_VREFDACS_SDA

7 SDA 9 A0

ADDR=0x98(WR)/0x99(RD)

C

10 A1

C3

27A5 VREFMRGN_DQ_SODIMMB_EN

B4

VREFMRGN_DQ_SODIMM

VOUTB 2

VREFMRGN_CA_SODIMM

VOUTC 4

VREFMRGN_CPUFSB

VOUTD 5

NC

VREFMRGN_DQ_SODIMMB_BUF

C4

V-

R2902

100K

5% 1/16W MF-LF 402

1

GND 3

U2903

B1

VREFMRGN

A2

C2904

V+

MAX4253

UCSP A1 VREFMRGN

0.1UF

20% 10V 2 CERM 402

A3

VREFMRGN_CA_SODIMMA_BUF

e r

VREFMRGN 16

C2902 0.1UF

20% 10V 2 CERM 402

VREFMRGN

VCC

P U2901

PCA9557 QFN

P0 P1 P2 P3 P4 P5 P6 P7

3

A0 A1 5 A2 4

42A3 42A3

IN BI

1

=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA

2

SCL SDA

THRM 17

PAD

A

NC

7 9

10 11 12 13

UCSP C1 VREFMRGN

20% 10V 2 CERM 402

R2908

100K

U2904

B1 A2

V+

5% 1/16W MF-LF 402

UCSP A1

27B3

VREFMRGN_DQ_SODIMMA_EN

27D3

R2911 200

VREFMRGN

2

1% 1/16W MF-LF 402

PP0V75_S3_MEM_VREFCA_B 29B3

R2912 1

100

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

VREFMRGN

2

1% 1/16W MF-LF 402

Place close to J3200.126

VREFMRGN

NC

A4

B U2904

B1 C2

V+

C3

R2914

MAX4253

VREFMRGN

UCSP C1

1

VREFMRGN_CPUFSB_BUF

B4

100

1% 1/16W MF-LF 402

C4

V-

27A5 VREFMRGN_CPUFSB_EN

5% 1/16W MF-LF 402

27C3


B4

100K

VREFMRGN_CA_SODIMMA_EN

2

1% 1/16W MF-LF 402

1

VREFMRGN

CPU_GTLREF

2

QTY

116S0004

1

OUT

10B4 71B3

Place close to U1000.AD26

VREFMRGN_CA_SODIMMB_EN

VREFMRGN

27B3

VREFMRGN_DQ_SODIMMB_EN

27C3

PCA9557D_RESET_L

IN

26C1

FSB/DDR3 Vref Margining SYNC_MASTER=BEN

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

RES,MTL FILM,0,5%,0402,SM,LF

R2903

CRITICAL

NO_VREFMRGN



Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

28B3


V-

R2913

VREFMRGN_CPUFSB_EN

100

C

PP0V75_S3_MEM_VREFCA_A

VREFMRGN

MAX4253

VREFMRGN A3

1

27A5 VREFMRGN_CA_SODIMMB_EN

B4

VREFMRGN

2

R2910

1

VREFMRGN_CA_SODIMMB_BUF

200

1% 1/16W MF-LF 402

C4

V-


R2909

VREFMRGN

MAX4253

2

1% 1/16W MF-LF 402

1

29D5


NC NC

14

RESET* 15

GND

V+

0.1UF

1

100

VREFMRGN

8

ADDR=0x30(WR)/0x31(RD)

6

C2

5% 1/16W MF-LF 402

PP0V75_S3_MEM_VREFDQ_B

R2906

1

B

C2905

U2903

B1

VREFMRGN

2

1

m il VREFMRGN

1

100K

200

1% 1/16W MF-LF 402

27A5 VREFMRGN_CA_SODIMMA_EN

R2907

C3

1

A4

V-

B4

1

VREFMRGN

1

42B3

IN

DAC5574

42B3

MAX4253

UCSP C1 VREFMRGN

VREFMRGN 8 U2900 VDD 1 MSOP VOUTA

5% 1/16W MF-LF 402

1

U2902

B1

2

20% 2 10V CERM 402

VREFMRGN

2

20% 6.3V CERM 402-LF

100K


R2905

a n i

0.1UF

2

2

1

2.2UF

100

28D5


VREFMRGN

2

C2900

1

1% 1/16W MF-LF 402

27A5 VREFMRGN_DQ_SODIMMA_EN

B4

VREFMRGN

VREFMRGN_DQ_SODIMMA_BUF

A4

V-

PP0V75_S3_MEM_VREFDQ_A

R2904

MAX4253

2

C2903

2

1% 1/16W MF-LF 402

U2902

B1

VREFMRGN 1

200

VREFMRGN


116S0004

1


R2905

CRITICAL

NO_VREFMRGN

116S0004

1


R2909

CRITICAL

NO_VREFMRGN

116S0004

1


R2911

CRITICAL

NO_VREFMRGN

SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 29

1

109

A

8

6

7

Page Notes

2

3

4

5

1

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8D3

=PP1V5_S3_MEM_A

Power aliases required by this page: - =PP1V5_S0_MEM_A 1

- =PP1V5_S3_MEM_A - =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V)

2

C3100

1

C3101

1

1

C3110

1

C3111

C3112

1

1

C3113

C3114

1

1

C3115

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R 603

20% 6.3V X5R 603

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

2

2

2

2

2

2

2

2

1

C3116

10UF

C3117 0.1UF 20%

2 6.3V X6S-CERM 0204-1

Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA BOM options provided by this page: 27D1

D

PP0V75_S3_MEM_VREFDQ_A

(NONE)

C3130

1

2

0.1UF

20% 6.3V CERM 402-LF

2

20% 10V CERM 402

1 73

MEM_A_CKE

NC 72D3 15C5

72D3 15C5

IN

72D3 15B5

IN

72D3 15B5

C

IN

IN

72D3 15B5

IN

72D3 15B5

IN

72D3 15B5

IN

72D3 15B5

IN

72D3 15B5

IN

72D3 15C5

IN

72D3 15C5

IN

72D3 15C5

IN

72D3 15C5

IN

72D3 15C5

IN

72D3 15B5

IN

MEM_A_BA

75 77 79 81 83

MEM_A_A MEM_A_A

85 87 89

MEM_A_A MEM_A_A

91 93 95

MEM_A_A MEM_A_A

97 99


101

MEM_A_A MEM_A_BA

107

MEM_A_WE_L MEM_A_CAS_L

113

MEM_A_A MEM_A_CS_L

119 121

103 105 109 111 115 117

123

NC 72D3 15C7

BI

72D3 15C7

BI

72C3 15D5

BI

72C3 15D5

BI

72D3 15C7

BI

72D3 15C7

BI

125 127

MEM_A_DQ MEM_A_DQ

129

MEM_A_DQS_N MEM_A_DQS_P

135

MEM_A_DQ MEM_A_DQ

141 143

131 133 137 139

145 147 149

72D3 15C7

BI

72D3 15C7

BI

MEM_A_DQ MEM_A_DQ

72C3 15B7

IN

MEM_A_DM

153 155

72D3 15C7

BI BI

MEM_A_DQ MEM_A_DQ

157

72D3 15C7

72D3 15D7

BI

72D3 15D7

BI

MEM_A_DQ MEM_A_DQ

163 165

151

B

159 161

167 72C3 15D5

BI

72C3 15D5

BI


169 171 173

72D3 15D7

BI

72D3 15D7

BI

MEM_A_DQ MEM_A_DQ

BI

72D3 15D7

BI

MEM_A_DQ MEM_A_DQ

72C3 15B7

IN

MEM_A_DM

72D3 15D7

BI

72D3 15D7

BI

MEM_A_DQ MEM_A_DQ

181 183 185 187 189 191 193 195

MEM_A_SA 8B5

=PPSPD_S0_MEM_A MEM_A_SA

197 199 201 203

1 1

A

C3140 2.2UF

2

20% 6.3V CERM 402-LF

2

1

R3140

R3141

10K

10K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

J3100

74

MEM_A_CKE

76 78

IN

15A5 72D3

72D3 15B7 72D3 15B7

MEM_A_A MEM_A_A

80 82 84

MEM_A_A MEM_A_A

86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122

138 140 142 144 146 148 150 152

154 156 158 160 162 164 166

72D3 15B7

BI

15B5 72D3

72D3 15B7

BI

72D3 15B7

BI

72C3 15D5

BI

IN

15B5 72D3

72C3 15D5

BI


IN

15B5 72D3

72D3 15B7

BI

IN

15B5 72D3

72D3 15B7

BI

MEM_A_BA MEM_A_RAS_L

IN

15C5 72D3

72D3 15C7

BI

IN

15C5 72D3

72D3 15C7

BI

MEM_A_CS_L MEM_A_ODT

IN

15B5 72D3

72C3 15D5

BI

IN

15A5 72D3

72C3 15D5

BI

MEM_A_ODT

IN

15A5 72D3

72D3 15C7

BI

15B5 72D3

72D3 15B7

MEM_A_DQ MEM_A_DQ MEM_A_DM MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

BI

3 5

MEM_A_DQ MEM_A_DQ

7 9 13 15

MEM_A_DQ MEM_A_DQ

17

19 21

MEM_A_DQ MEM_A_DQ

23 25 27


29 31 33

MEM_A_DQ MEM_A_DQ

35 37 39

MEM_A_DQ MEM_A_DQ

41 43 45

MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQ MEM_A_DQ

BI

15C7 72D3

BI

15C7 72D3

IN

BI

15C7 72D3

BI

15C7 72D3

BI

15C7 72D3

BI

15C7 72D3

BI

15D5 72C3

BI

15D5 72C3

BI

15C7 72D3

BI

15C7 72D3

BI

15D7 72D3

BI

15D7 72D3

IN

72D3 15B7

BI

72D3 15B7

BI

MEM_A_DQ MEM_A_DQ

IN

MEM_A_DM

72D3 15C7

BI

72D3 15B7

BI

MEM_A_DQ MEM_A_DQ

72C3 15A7

15A7 72C3

BI

VREFDQ VSS VSS DQ4 DQ5 DQ0 CRITICAL VSS DQ1 VSS DQS0* DQS0 DM0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DQS1* DM1 RESET* DQS1 VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 VSS DQ19 DQ28 VSS DQ24 DQ29 VSS DQ25 DQS3* VSS DQS3 DM3 VSS VSS DQ30 DQ26 DQ31 DQ27 VSS VSS

J3100

2 4 6

MEM_A_DQ MEM_A_DQ

8 10

BI

15B7 72D3

BI

15B7 72D3


BI

15D5 72C3

BI

15D5 72C3

MEM_A_DQ MEM_A_DQ

BI

15B7 72D3

BI

15B7 72D3

MEM_A_DQ MEM_A_DQ

BI

15B7 72D3

MEM_A_DM MEM_RESET_L

IN

15A7 72C3

IN

29C2 30C3

a n i 11

MEM_A_DM

47 49

m il 72D3 15C7

174

186 188

15C5 72D3

IN

15B5 72D3

MEM_A_DM

182 184

IN

15B5 72D3

170 172

180

IN

IN

168

176 178

72C3 15A7

IN

126 128

136

15C5 72D3

MEM_A_A MEM_A_A

NC

132 134

9D2

IN

BI

IN

124

130

IN

BI

MEM_A_A MEM_A_A

e r

P 175 177 179

72D3 15D7

CKE0 CKE1 VDD VDD NC A15 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD WE* S0* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DM4 DQS4* DQS4 VSS DQ38 VSS DQ39 DQ34 DQ35 VSS VSS DQ44 DQ45 DQ40 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 VSS DQS6 DQ54 VSS DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SCL SA1 VTT VTT (SYMBOL 2 OF 2)

IN

DDR3-SODIMM-DUAL-M97-3

72D3 15A5

KEY

y r

C3131

2.2UF

51 53 55 57 59 61 63 65 67 69 71

(SYMBOL 1 OF 2)

1

DDR3-SODIMM-DUAL-M97-3

D

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

BI

15B7 72D3

MEM_A_DQ MEM_A_DQ

BI

15B7 72D3

BI

15B7 72D3

MEM_A_DQ MEM_A_DQ

BI

15C7 72D3

BI

15C7 72D3

MEM_A_DM

IN

MEM_A_DQ MEM_A_DQ

BI

15C7 72D3

BI

15C7 72D3

MEM_A_DQ MEM_A_DQ

BI

15B7 72D3

BI

15B7 72D3


BI

15D5 72C3

BI

15D5 72C3

MEM_A_DQ MEM_A_DQ

BI

15B7 72D3

BI

15C7 72D3

C

15A7 72C3

KEY

516-0201

B

15B7 72C3

BI

15D7 72D3

BI

15D7 72D3

BI

15D7 72D3

BI

15D7 72D3

PP0V75_S3_MEM_VREFCA_A

1

C3135

1

2.2UF


BI

15D5 72C3

BI

15D5 72C3

MEM_A_DQ MEM_A_DQ

BI

15D7 72D3

BI

15D7 72D3

2

20% 6.3V CERM 402-LF

27C1

C3136 0.1UF

2

20% 10V CERM 402

190 192 194 196 198 200 202

MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

OUT

21A4 21B3 29A5 39B8

BI IN

"Factory" (top) slot

42D6 42D6

204

=PP0V75_S0_MEM_VTT_A

8C7

DDR3 SO-DIMM Connector A 1

2

C3150

1

C3151

2.2UF

2.2UF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

2

SYNC_MASTER=BEN


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

516-0201


SPD ADDR=0xA0(WR)/0xA1(RD) SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 31

1

109

A

8

6

7

Page Notes

2

3

4

5

1

DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE) 8D3

=PP1V5_S3_MEM_B

Power aliases required by this page: - =PP1V5_S0_MEM_B 1

- =PP1V5_S3_MEM_B - =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V)

2

C3200

1

C3201

1

1

C3210

1

C3211

C3212

1

1

C3213

C3214

1

1

C3215

10UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20% 6.3V X5R 603

20% 6.3V X5R 603

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

2

2

2

2

2

2

2

2

1

C3216

10UF

C3217 0.1UF 20%

2 6.3V X6S-CERM 0204-1

Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA BOM options provided by this page: 27C1

D

PP0V75_S3_MEM_VREFDQ_B

(NONE)

C3230

1

2

0.1UF

20% 6.3V CERM 402-LF

2

20% 10V CERM 402

1 73

203

CKE0 CKE1 VDD VDD NC A15 A14 BA2 VDD F-RT-BGA3 VDD A11 A12/BC* A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK1 CK0 CK0* CK1* VDD VDD A10/AP BA1 RAS* BA0 VDD VDD S0* WE* CAS* ODT0 VDD VDD ODT1 A13 S1* NC VDD VDD TEST VREFCA VSS VSS DQ36 DQ32 DQ37 DQ33 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS EVENT* SA0 VDDSPD SDA SA1 SCL VTT VTT

205 207

MTG PIN MTG PIN

209 211

MTG PIN MTG PIN

75 77 72B3 15C1

72B3 15C1

IN

72B3 15B1

IN

72B3 15B1

C

MEM_B_A MEM_B_A MEM_B_A MEM_B_A

IN

72B3 15B1

IN

72B3 15B1

IN

72B3 15B1

IN

72B3 15B1

IN

72B3 15B1

IN

72B3 15C1

IN

72B3 15C1

IN

72B3 15C1

IN

72B3 15C1

IN

72B3 15C1

IN

72B3 15B1

MEM_B_BA

IN

MEM_B_A MEM_B_A

IN

79 81 83 85 87 89 91 93 95 97 99


101

MEM_B_A MEM_B_BA

107

MEM_B_WE_L MEM_B_CAS_L

113

MEM_B_A MEM_B_CS_L

119 121

103 105 109 111 115 117

123 125 127 72B3 15C3

BI

72B3 15C3

BI

72A3 15D1

BI

72A3 15D1

BI

72B3 15C3

BI

72B3 15C3

BI

MEM_B_DQ MEM_B_DQ

129

MEM_B_DQS_N MEM_B_DQS_P

135

MEM_B_DQ MEM_B_DQ

141 143

131 133 137 139

145 147 149

72B3 15C3

BI

72B3 15C3

BI

MEM_B_DQ MEM_B_DQ

72B3 15B3

IN

MEM_B_DM

153 155

72B3 15C3

BI BI

MEM_B_DQ MEM_B_DQ

157

72B3 15C3

72B3 15D3

BI

72B3 15D3

BI

MEM_B_DQ MEM_B_DQ

163 165

151

B

159 161

167 72A3 15D1

BI

72A3 15D1

BI


169 171 173

72B3 15D3

BI

72B3 15D3

BI

72B3 15D3

BI

72B3 15D3

BI

MEM_B_DQ MEM_B_DQ

1

R3240

72A3 15B3

IN

MEM_B_DM

72B3 15D3

BI

72B3 15D3

BI

MEM_B_DQ MEM_B_DQ

2

185 187 189

10K 5% 1/16W MF-LF 402

181 183

191 193 195

MEM_B_SA 8B5

=PPSPD_S0_MEM_B MEM_B_SA

1 1

A

C3240

2

R3241 10K

2.2UF 20% 6.3V CERM 402-LF

2

5% 1/16W MF-LF 402

197 199 201

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122

MEM_B_CKE

IN

MEM_B_A MEM_B_A

136 138 140 142 144 146 148 150

MTG PINS

MTG PIN

MTG PIN

MTG PIN

MTG PIN

152

154 156 158 160 162 164 166

174 176 178 180 182 184 186 188

9D2

IN

15C1 72B3

72B3 15A3

BI

IN

IN

15C1 72B3

72B3 15B3

BI

IN

15B1 72B3

72B3 15B3

BI

IN

15B1 72B3

72B3 15B3

BI

MEM_B_A MEM_B_A

IN

15B1 72B3

72A3 15D1

BI

IN

15B1 72B3

72A3 15D1

BI


IN

15B1 72B3

72B3 15B3

BI

IN

15B1 72B3

72B3 15B3

BI

MEM_B_BA MEM_B_RAS_L

IN

15C1 72B3

72B3 15B3

BI

IN

15C1 72B3

72B3 15B3

BI

MEM_B_CS_L MEM_B_ODT

IN

15B1 72B3

72A3 15D1

BI

IN

15A1 72B3

72A3 15D1

BI

MEM_B_ODT

IN

15A1 72B3

72B3 15C3

BI

72B3 15B3

15B1 72B3

MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ

MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ

BI

3 5

MEM_B_DQ MEM_B_DQ

7 9

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQ MEM_B_DQ

BI

15C3 72B3

BI

15C3 72B3

IN

BI

15C3 72B3

BI

15C3 72B3

BI

15C3 72B3

BI

15C3 72B3

BI

15D1 72A3

BI

15D1 72A3

BI

15C3 72B3

BI

15C3 72B3

BI

15D3 72B3

BI

15D3 72B3

IN

72B3 15C3

BI

72B3 15C3

BI

MEM_B_DQ MEM_B_DQ

IN

MEM_B_DM

72B3 15C3

BI

72B3 15C3

BI

MEM_B_DQ MEM_B_DQ

72B3 15A3

15A3 72B3

BI

VREFDQ VSS VSS DQ4 DQ5 DQ0 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ14 DQ10 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 VSS DQ19 VSS DQ28 DQ29 DQ24 VSS DQ25 DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS

J3200

2 4 6 8 10

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

15D3 72B3

BI

15D3 72B3

BI

15D3 72B3

BI

15D3 72B3

C3235

1

2.2UF


BI

15D1 72A3

BI

15D1 72A3

MEM_B_DQ MEM_B_DQ

BI

15D3 72B3

BI

15D3 72B3

2

20% 6.3V CERM 402-LF

15B3 72B3

BI

15B3 72B3


BI

15D1 72A3

BI

15D1 72A3

MEM_B_DQ MEM_B_DQ

BI

15B3 72B3

BI

15B3 72B3

MEM_B_DQ MEM_B_DQ

BI

15B3 72B3

MEM_B_DM MEM_RESET_L

IN

15A3 72B3

IN

28C2 30C3

MEM_B_DQ MEM_B_DQ

BI

15B3 72B3

BI

15B3 72B3

MEM_B_DQ MEM_B_DQ

BI

15B3 72B3

BI

15B3 72B3

MEM_B_DM

IN

MEM_B_DQ MEM_B_DQ

BI

15B3 72B3

BI

15C3 72B3

MEM_B_DQ MEM_B_DQ

BI

15C3 72B3

BI

15C3 72B3


BI

15D1 72A3

BI

15D1 72A3

MEM_B_DQ MEM_B_DQ

BI

15C3 72B3

BI

15C3 72B3

BI

15B3 72B3

C

15A3 72B3

516S0706

B DDR3 GROUND RETURN CAPS (MCP SIDE) 8B7

=PP1V5_S0_MEM_MCP

1

2

PP0V75_S3_MEM_VREFCA_B

1

BI

KEY

15B3 72A3

BI

MEM_B_DQ MEM_B_DQ

a n i

MEM_B_DM

m il 72B3 15B3

168 170 172

IN

BI

IN

126 128 132 134

72B3 15B3

MEM_B_A MEM_B_A

124

130

15A1 72B3

72B3 15B3

MEM_B_A MEM_B_A

e r

P 175 177 179

MEM_B_DQ MEM_B_DQ

J3200 (2 OF 2)

MEM_B_CKE

IN

DDR3-SODIMM

72B3 15A1

KEY

y r

C3231

2.2UF

(1 OF 2)

1

DDR3-SODIMM

D

27C1

C3222

1

C3223

1

C3224

1

C3225

1

C3226

1

C3227

1

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

20% 6.3V X6S-CERM 0204-1

2

2

2

2

2

2

1

C3228

0.1UF

C3229 0.1UF 20%

2 6.3V X6S-CERM 0204-1

C3236 0.1UF

2

20% 10V CERM 402

190 192 194 196 198 200 202

MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

OUT

21A4 21B3 28A5 39B8

BI IN

42D6

"Expansion" (bottom) slot

42D6

204

=PP0V75_S0_MEM_VTT_B

8C7

DDR3 SO-DIMM Connector B

206 208

1

210 212

2

C3250

1

C3251

2.2UF

2.2UF

20% 6.3V CERM 402-LF

20% 6.3V CERM 402-LF

2

SYNC_MASTER=BEN


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

516S0706 SIZE

SPD ADDR=0xA2(WR)/0xA3(RD)

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 32

1

109

A

8

7

6

2

3

4

5

1

D

D

y r

a n i

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

8D3

8A3

=PP1V5_S3_MEMRESET 3.3V input must be stable before before 1.5V starts to rise to avoid glitch on MEM_RESET_L.

=PP3V3_S5_MEMRESET

1

1K

MEMRESET_HW

C

R3310

1

2

R3305

5% 1/16W MF-LF 402

MEM_RESET_L

20K

MEMRESET_HW

R3300 1

2

MEM_RESET

10K 5% 1/16W MF-LF 402

MEMRESET_HW 3

2

R3301 1

Q3305

5

MMDT3904-X-G

4

C3300 0.1UF

2 2

R3309 0

MMDT3904-X-G 1

C

28C2 29C2

2

5% 1/16W MF-LF 402

m il

MEMRESET_HW 1

20K

IN

1

Q3305

SOT-363-LF

MEMRESET_HW

16C3

MEMRESET_HW 6 2

OUT

MEMRESET_MCP

SOT-363-LF

MEM_RESET_RC_L

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

20% 10V CERM 402

MCP_MEM_RESET_L

e r

B

P

A

B

DDR3 Support SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 33

1

109

A

8

6

7 17C6 9C6

OUT

2

3

4

5

1

PCIE_MINI_PRSNT_L 3

D

Q3401 SSM6N15FEAPE SOT563

4

S

G

5

AP_PWR_EN

21A3 21B3 34C7

IN

5V S3 WLAN FET

D D

Q3401

CHANNEL

P-TYPE

RDS(ON)

D

y r

26 mOhm @4.5V

SSM6N15FEAPE SOT563

S

G

0.8 A (EDP)

2

Q3450

a n i

L3404

1

20347-325E-12

2

10%

2

PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N

0.1uF

16V X5R 402

7D5 7C3

IN

17B3 73D3

IN

17B3 73D3

16V X5R 402

2

PP5V_WLAN

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

1 2

OUT

7D5 17B6 73D3

OUT

7D5 17B6 73D3

3 4

73D3 7D5

5

73D3 7D5

PCIE_CLK100M_MINI_CONN_P 7D5 PCIE_CLK100M_MINI_CONN_N

73D3 7D5

8

73D3

7C5

11

2

1

PCIE_CLK100M_MINI_N

2

OUT

IN

17C3 73D3

7D5 17B6 23C5

m il

14

17

NC NC 7D5

18 19

PP5V_S3_BTCAMERA_F I2C_ALS_SDA I2C_ALS_SCL

BI IN

42D1

22

74C3

ALS CAMERA

CRITICAL

23

L3402 90-OHM

CONN_USB2_BT_P CONN_USB2_BT_N

24 25

DLP0NS SYM_VER-1

4

3

27 1 28

30

L3403 90-OHM

USB_CAMERA_N

OUT

20D3 74C3

SYM_VER-1

1

P =PP3V3_S3_WLAN

TC7SZ08AFEAPE 5 SOT665

MINI_RESET_CONN_L

4

A

U3401

Y

B

2

3

USB_BT_P

BI

20C3 74B3

2

USB_BT_N

BI

20C3 74B3

PLACEMENT_NOTE=Place close to J3401.

PP5V_WLAN_F

8D3

1

5 6

2

2

20% 10V X5R 805

C3450 0.1UF 2

10% 16V X5R 402

C3451

1

10% 16V X5R 402

P5VWLAN_SS

R3451 10K

0.033UF

2

R3450

1

100K

2

5% 1/16W MF-LF 402

PM_WLAN_EN_L

2

IN

34C6

5% 1/16W MF-LF 402

C

1

2

=PP5V_S3_BTCAMERA

8C3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

B

31C3

R3453 33K

U3402

5

74LVC1G17DRL

2

SOT-553 4

WLAN_SMIT_BUF

5% 1/16W MF-LF 402

2

WLAN_SMIT_RC

NC

1

3

MINI_RESET_L

1

NC

3

A

20% 10V CERM 402

20D3 74C3

DLP0NS

4

7C5

10UF

8C3

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

BLUETOOTH

CRITICAL

32

1

0402-LF

0.1uF

OUT


29

B

2

C3452

USB_CAMERA_P

e r

26

2

FERR-120-OHM-1.5A

42D1

USB_CAMERA_CONN_P 7D5 USB_CAMERA_CONN_N

74C3 7D5

L3405

275 mA peak 206 mA nominal max


20 21

C3420

=PP5V_S3_WLAN

PLACEMENT_NOTE=Place close to Q3450.

13

16

1

1

PLACEMENT_NOTE=Place close to Q3450.

IN

17C3 73D3

12

15

SOT-6

1


MINI_CLKREQ_Q_L PCIE_WAKE_L

PP5V_WLAN_F


PCIE_CLK100M_MINI_P

3

9 10

20% 10V CERM 402

SYM_VER-1

4

1

0.1uF

AIRPORT

DLP11S

6 7

20% 10V CERM 402

L3401 90-OHM-100MA

PCIE_MINI_R2D_P PCIE_MINI_R2D_N

C3421

1

0.1uF

CRITICAL

31A5


C3422 PLACEMENT_NOTE=Place close to J3401.

31

1


C3430

F-RT-SM

C

10%

0.1uF

1000 mA peak 750 mA nominal max

G

1

J3401

0402-LF

2

C3431

FDC606P_G

FERR-120-OHM-1.5A


1

CRITICAL 518S0610

D

1

LOADING

4

6

FDC606P

S

OUT

MOSFET

3

17C6

MINI_CLKREQ_L

1

C3453 IN

26C1

1

10% 6.3V CERM 402

Right Clutch Connector

R3454 62K

1UF 2 2

SYNC_MASTER=YITE

5% 1/16W MF-LF 402



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 34

1

109

A

8

6

7

2

3

4

5

1

D

D

y r

a n i

CRITICAL

J3501

503219-0221 M-ST-SM

C

24

VENICE

9C5

OUT FC_CLKREQ_L

73D3 9B5

73D3 9B5

IN

73D3 9B5

IN

PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N

PLACEMENT_NOTE=Place close to J3501. 73C3 C3573 VENICE 1 2 0.1uF 1 2 0.1uF 10% 16V X5R 402 10%

IN

9B5

IN

PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N

PCIE_FC_R2D_P 73D3 PCIE_FC_R2D_N

23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

m il

16V X5R 402

73D3

15

16

9B5

OUT PCIE_FC_D2R_P

17

18

73D3 9B5

OUT PCIE_FC_D2R_N

19

20

21

22

C3572 VENICE 73D3 PLACEMENT_NOTE=Place close to J3501.

25 26

C

NC

=PP3V3_FC_CON

8B5

=PP1V5_FC_CON

8B7

NC NC NC

FC_PRSNT_L FC_RESET_L

OUT

9C5

OUT

26C1

Venice Connector

e r

B

P

A

B

VENICE CONNECTOR SYNC_MASTER=YITE



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 35

1

109

A

8

6

7

2

3

4

5

=PP1V05_ENET_PHY

D

C3710

C3711

1

0.1UF 8B1

10% 16V X5R 402

=PP3V3_ENET_PHY

1

1

0.1UF 10% 16V X5R 402

2

1

1

CRITICAL

L3705

2

FERR-120-OHM-1.5A

C3700

1

C3701

1

L3715 FERR-120-OHM-1.5A

C3702

0.1UF

0.1UF

0.1UF

10% 16V X5R 402

10% 16V X5R 402

10% 16V X5R 402

2

2

2

PP1V05_ENET_PHYAVDD

C3714

0402-LF

C3715

1

0.1UF 10% 16V X5R 402

2

0.1UF 10% 16V X5R 402

2

1

C3705

1

0.1UF 2

C3706 0.1UF

10% 16V X5R 402

2

1


0.1UF 10% 16V X5R 402

2

2

a n i

PP3V3_ENET_PHYAVDD MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

C3716

1

10% 16V X5R 402

D

y r

CRITICAL 2

8B1

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect) WF: Marvell numbers, update for Realtek

0402-LF

(43mA typ - 1000base-T) (19mA typ - Energy Detect) WF: Marvell numbers, update for Realtek

1

=PP3V3_ENET_PHY_VDDREG

9D2

If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

9D2

2

=RTL8211_ENSWREG

39

IN

ENSWREG

10 40

3

44 45

15 21 37

OMIT CRITICAL

AVDD12

5% 1/16W MF-LF 402

28 36

4.7K

FB12

5% 1/16W MF-LF 402 2

DVDD12

Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.

VDDREG

10K

C

R3725

DVDD33

1

AVDD33

NO STUFF

R3720 1

6 41

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

U3700 RTL8211CLGR

R3750 1 5% 1/16W MF-LF 402

REGOUT

RXC

19

TQFP ENET_CLK125M_TXCLK

1

0

2

75D3

22

ENET_CLK125M_TXCLK_R

5% 1/16W 402 MF-LF

PLACE R3796 CLOSE TO U1400, PIN D24

IN

ENET_TXD ENET_TXD ENET_TXD ENET_TXD

IN

ENET_TX_CTRL

75D3 18C3

IN

75D3 18C3

BI

ENET_MDC ENET_MDIO

75C3 18D3

IN

75C3 18D3

IN

75C3 18D3 75C3 18D3

75C3 18C3

IN

IN

ENET_RESET_L

1

0

RTL8211_PHYRST_L

2

5% 1/16W MF-LF 402

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE. HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

1

e r

C3725 0.1UF

NO STUFF

2

RTL8211_RSET

20% 10V CERM 402

B

TP_RTL8211_CLK125

R3730 1 2.49K 1% 1/16W MF-LF 402

75D3 34A3

IN

2

P

A

RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2

14 16 17 18

m il

R3724 75C3 18C3

23 24 25 26

TXC

27

30 31

29

46

32

TXD[0] TXD[1] TXD[2] TXD[3]

RGMII/MII

TXCTL

MDC MDIO

PHYRSTB*

RSET

RXCTL

4.7K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

13

MDI+[0] MDI-[0]

1 2

MDI+[1] MDI-[1]

75D3

=RTL8211_REGOUT

9D2

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

2

75D3 75D3 75D3 75D3

75D3

R3790

ENET_CLK125M_RXCLK_R

R3791 R3792 R3793 R3794

ENET_RXD_R ENET_RXD_R ENET_RXD_R ENET_RXD_R

R3795

ENET_RXCTL_R

BI

35B7 75C3

BI

35B7 75C3

4 5

ENET_MDI_P ENET_MDI_N

BI

35C7 75C3

BI

35C7 75C3

MDI+[2] MDI-[2]

8 9


BI

35B7 75C3

BI

35C7 75C3

MDI+[3] MDI-[3]

11 12


BI

35C7 75C3

BI

35C7 75C3

LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY

34 35 38

RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY

RESET MEDIA DEPENDENT

REFERENCE

2

4.7K


MANAGEMENT

C

22

22 22 22 22

22

1

1

2

1

2

1

2

1

2

1

ENET_CLK125M_RXCLK

2 5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

ENET_RXD ENET_RXD ENET_RXD ENET_RXD

ENET_RX_CTRL

2

OUT

18D6 75D3

OUT

18D6 75D3

OUT

18D6 75D3

OUT

18D6 75D3

OUT

18D6 75D3

OUT

18D6 75D3

B

CLK125

CLOCK

42 43

RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1

CKXTAL1 CKXTAL2

LED

GND

7 20 33 47

IN

2

R3752 1

R3751

If internal switcher is not used, VDDREG and REGOUT can float.

48

R3796 75D3 18D3

1

4.7K

NO STUFF

C3790

1

10PF 5% 50V CERM 402

2

R3755 1

R3756 1

4.7K

4.7K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

1

R3757 4.7K

2

2

5% 1/16W MF-LF 402

Reserved for EMI per RealTek request.

Ethernet PHY (RTL8211CL) SYNC_MASTER=SUMA


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Configuration Settings: SIZE

PHYAD AN[1:0] RXDLY TXDLY

= = = =

01 11 0 0

8

DRAWING NUMBER

D

(PHY Address 00001) (Full auto-negotiation) (RXCLK transitions with data) (No TXCLK Delay)

APPLE INC.

SCALE

SHT NONE

7

6

5

4

3

2

REV.

051-7537

A

OF 37

1

109

A

8

6

7

2

3

4

5

1

3.3V ENET FET @ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)

CRITICAL

Q3810 NTR4101P SOT-23-HF

8A3

=PP3V3_S5_P3V3ENETFET

=PP3V3_ENET_FET

S

2

D

1

R3800 1 5% 1/16W MF-LF 402

2

R3810

2

D

3

S

4

1

D

G

10% 16V X5R 402

y r

1

C3810

P3V3ENET_SS

2

2

5% 1/16W MF-LF 402

1

10% 16V CERM 402

SSM6N15FEAPE SOT563

5

9D2

IN

G

a n i

=P3V3ENET_EN

MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.

WLAN Enable Generation "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. PM_WLAN_EN_L

C

31C1

OUT

1.05V ENET FET

Pull-up is with power FET.

Q3805

D

6

SSM6N15FEAPE SOT563

2

31D5 21B3 21A3

IN

G

8B3

S

1.8V Vgs

C3840

3

6

D

SSM6N15FEAPE

m il 8A3

Q3801 SSM6N15FEAPE

SOT563

SOT563

=PP3V3_S5_P1V05ENETFET

R3842 1

5

40B2 39D5 21C7

68D8 64D5 41A5 39C5 21C3 7C3

IN

IN

G

S

4

1

S

G

69.8K

2

1% 1/16W MF-LF 402

SMC_ADAPTER_EN

2

PM_SLP_S3_L

Q3841

e r

B

P

D

3

S

4

20% 10V CERM 402

R3840 100K

1

3

CRITICAL

D

2

Q3840

P1V05ENET_SS

2

1

SI2312BDS

G

SOT23

S

5% 1/16W MF-LF 402

P1V05ENET_EN_L

A

1

0.1UF

AC_OR_S0_L

Q3805

C

=PP1V05_ENET_P1V05ENETFET

1

AP_PWR_EN

D

8B2

3

0.01UF

100K

P3V3ENET_EN_L

Q3801

C3811 0.033UF

10K

D

Q3841

D

6

2

=PP1V05_ENET_FET

SSM6N15FEAPE

8B2

SOT563

R3841

2

G

S

1

1

2 2 1% 1/16W MF-LF 402

C3841 0.01UF

10K

1

10% 16V CERM 402

P1V05ENET_EN_L_RC

SSM6N15FEAPE SOT563

5

9D2

IN

G

B

=P1V05ENET_EN

Non-ARB:

Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on ARB for alternate power options.

RTL8211 25MHz Clock

Ethernet & AirPort Support

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

SYNC_MASTER=SUMA



R3895 75D3 18C3

IN

MCP_CLK25M_BUF0_R

22 1

2

RTL8211_CLK25M_CKXTAL1

OUT


33B6 75D3

5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 38

1

109

A

8

6

7

2

3

4

5

1

- COPY THIS PAGE FROM K36 CSA.39

D

D

y r

PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902

ENET_CONN_CTAP 1

C3900 0.1UF

1

C3901

1

0.1UF

C3902

C3903

1

0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

ETHERNET CONNECTOR

0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

a n i

CRITICAL

75C3 33B3

75C3 33B3

BI

BI


T3901 SM

1

12

2

11

3

10

75C3

75C3

1% 1/16W 9

1% 1/16W 75C3 33B3

75C3 33B3

BI

BI


5

MF-LF 402

R3902 2 75 ENET_CENTER_TAP 1

TLA-6T213HF

C

MF-LF

402

8

6

ENET_MDI_TRAN_N

R3903 2 75

ENET_CENTER_TAP 1

TX

4

ENET_MDI_TRAN_P

75C3

7

75C3

ENET_MDI_TRAN_P ENET_MDI_TRAN_N

RX

CRITICAL

75C3 33B3

75C3 33B3

BI

ENET_MDI_N

1

BI

ENET_MDI_P

2

T3902 SM

TLA-6T213HF 4

9 8

BI

ENET_MDI_N

5

75C3 33B3

BI

ENET_MDI_P

6

7 RX

P

A

MF-LF 402

R3900 2 75

F-RT-TH 9

10

1 2 3 4 5

C

6 7 8

11 12

514-0596

MF-LF 402

75C3

ENET_MDI_TRAN_N

75C3

ENET_MDI_TRAN_P

ENET_BOB_SMITH_CAP

e r

B

ENET_MDI_TRAN_N

ENET_MDI_TRAN_P

ENET_CENTER_TAP 1

1% 1/16W

75C3 33B3

75C3

75C3

R3901 2 75

10 ENET_CENTER_TAP 1 1% 1/16W

TX

RJ45-M97-2

m il

12 11

3

CRITICAL

J3900

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL

1

C3910 1000PF

B

10% 2KV 2 CERM 1206

ETHERNET CONNECTOR SYNC_MASTER=SUMA



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 39

1

109

A

8

6

7

2

3

4

5

1

ODD Power Control CRITICAL

Q4590 6

FDC606P_G D

7C3 7B7

PP5V_SW_ODD

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

D

1

S

D

2 5

SOT-6

=PP5V_S0_ODD 4

8D5

36B7 8C5

1

100K

0.068UF

5% 1/16W MF-LF 402

=PP3V3_S0_ODD

R4595 ODD_PWR_EN_LS5V_L

R4597

1

D 6

Q4596

10% 10V 2 CERM 402

100K 2

y r

C4596 0.01UF 1

ODD_PWR_SS

5% 1/16W MF-LF 402

100K 5% 1/16W MF-LF 402

C4595

G

R4596

3

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

2

10% 16V CERM 402

SSM6N15FEAPE SOT563

ODD_PWR_EN G

2

Q4596

S 1

D 3

a n i

SSM6N15FEAPE SOT563

5 21B3

IN

G

S 4

ODD_PWR_EN_L

C

SATA ODD Port FL4520 90-OHM-100MA

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

DLP11S SYM_VER-1

CRITICAL 3

4

73A3

1

SATA_ODD_R2D_UF_P

0.01UF

2

J4500

CRITICAL

36D5 8C5

M-ST-SM-LF

=PP3V3_S0_ODD

R45901 33K

5% 1/16W MF-LF 402 2

2

1

4

3

6

5

OUT

73A3 7C5

8

7

10

9

73A3 7B7

12

11

73A3 7B7

14

13

16

15

SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P

B CRITICAL

1

C4501

1

0.1UF

J4501

20% 2 10V CERM 402

20374020E31 F-ST-SM 21

0.1UF

P CRITICAL

L4500

C4525 1

C4502

20% 2 10V CERM 402

0.01UF

C4521

10% 16V

2

SATA_ODD_R2D_C_P

IN

20D6 73A3

SATA_ODD_R2D_C_N

IN

20D6 73A3

CERM 402

C4520

10% 16V

CERM 402

FL4525

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

C4526 1

e r

Indicates disc presence

1

SATA_ODD_R2D_UF_N

2

PLACEMENT_NOTE=Place FL4520 close to J4500

0.01UF

SMC_ODD_DETECT

73A3

SATA_ODD_R2D_P 7B7 SATA_ODD_R2D_N

73A3 7B7

516S0617 39B8 7B7

1

m il

55560-0168

C

0.01UF

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

2

73A3

90-OHM-100MA DLP11S SYM_VER-1

CRITICAL 3 SATA_ODD_D2R_N

4

SATA_ODD_D2R_UF_N

OUT

20D6 73A3

OUT

20D6 73A3

10% 16V CERM 402

2

73A3

1

SATA_ODD_D2R_UF_P

2

SATA_ODD_D2R_P

10% 16V CERM 402


B

SATA HDD Port

FERR-70-OHM-4A

1

7C5 7C3

PP5V_S0_HDD_FLT

2

6 7 8 9

NC NC

3

73A3 7C5

SATA_HDD_R2D_P

73A3 7C5

SATA_HDD_R2D_N

2

NC

12

16 17

73A3 7C5

SATA_HDD_D2R_C_N

73A3 7C5

SATA_HDD_D2R_C_P

NC

14

A

8D5

PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510

DLP11S SYM_VER-1

4

1

73A3

73A3

C4510 1

SATA_HDD_R2D_UF_P

0.01UF

C4511 1

SATA_HDD_R2D_UF_N

0.01UF


11

15

=PP5V_S0_HDD

FL4501 90-OHM-100MA

CRITICAL

10

13

2

0603

4 5

1

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

3

C4515 1 0.01UF

C4516 1

NC NC

0.01UF

18

2

SATA_HDD_R2D_C_P

IN

20D6 73A3

IN

20D6 73A3

OUT

20D6 73A3

10% 16V CERM 402 2

SATA_HDD_R2D_C_N

10% 16V CERM 402

FL4502

90-OHM-100MA DLP11S SYM_VER-1

2 10% 16V 2 10% 16V

73A3

SATA_HDD_D2R_UF_N

CRITICAL

4

3

1

2

SATA_HDD_D2R_N

SATA Connectors

CERM 402 73A3

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_P

SYNC_MASTER=CHANGZHANG OUT


PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501

19


20D6 73A3

CERM 402


20


22


518S0654

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 45

1

109

A

8

6

7

2

3

4

5

1

D

D

USB PORT A (FRONT PORT)

PLACEMENT_NOTE=NEAR J4600 CRITICAL

CRITICAL

L4605

U4690

FERR-220-OHM-2.5A

TPS2064DGN USB_EXTA_OC_L

8

OUT

IN

OUT

1

1

10UF

C4691 0.1UF

20% 6.3V X5R 603

2

2

20% 10V CERM 402

PP5V_S3_RTUSB_B_ILIM

0

1

=USB_PWR_EN

STUFF R4691 IF USING TPS2060(ACTIVE LOW ENABLE) STUFF R4690 IF USING TPS2064(ACTIVE HIGH ENABLE)

1

10UF 20% 6.3V X5R 603

1

C4696 100UF

2

CRITICAL

B

1

C4650

1

20% 2 6.3V POLY-TANT CASE-B2-SM

0 5% 1/16W MF-LF

2

41C3 40B2 39C5 39B8 41C5 40B2 39C5 39B8

IN OUT

VCC SMC_DEBUG_YES

SMC_RX_L SMC_TX_L

5 M+ 4 M-

USB_EXTA_P USB_EXTA_N

7 D+ 6 D-

U4650

Y+ 1 Y- 2

PI3USB102ZLE 74C3 20D3 74C3 20D3

BI BI

8

TQFN

CRITICAL SEL 10

OE* 3

SMC_DEBUG_NO

R4651 1

0 5% 1/16W MF-LF 402

USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB

GND

A

5% 1/16W MF-LF 402

2

SMC_DEBUG_NO

1

C4616 100UF

20% 6.3V X5R 603

e r

P 2

9

20% 10V CERM 402

R4650 10K

0.1UF

1

10UF

R4691

=PP3V42_G3H_SMCUSBMUX SMC_DEBUG_YES

USB_EXTA_MUXED_N

m il

C4617

1NOSTUFF

USB/SMC Debug Mux 8D1

74C3

2

2

74C3

USB_EXTA_MUXED_P

20% 6.3V POLY-TANT CASE-B2-SM

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

2 402

IN

0

USB F-RT-TH-M97-3 5

L4600 90-OHM

4

3

1

2

74C3

CONN_USB_EXTA_N

6

74C3

CONN_USB_EXTA_P

2

6 VBUS

3

5

1 2 3 4

4

7 8

514-0606

1 GND

D4600

RCLAMP0502N SLP1210N6

PLACEMENT_NOTE=NEAR J4610 CRITICAL CRITICAL We can add protection to 5V if we want, but leaving NC for now

L4615

FERR-220-OHM-2.5A 1

2 0603

1

C4615

Place L4600 and L4605 at connector pin

PP5V_S3_RTUSB_B_F MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

B

0.01uF 2

20% 16V CERM 402

CRITICAL

J4610 USB F-RT-TH-M97-3 5


6

L4610 90-OHM DLP0NS

1

SYM_VER-1

74B3 20C3

BI

USB_EXTB_N

4

3

74B3 74B3

CONN_USB_EXTB_N CONN_USB_EXTB_P

2 3 4

74B3 20C3

BI

USB_EXTB_P

1

2 7 2 6 VBUS

5

3

4

8

514-0606

1 GND

39B8

D4610 RCLAMP0502N SLP1210N6

External USB Connectors

CRITICAL

SYNC_MASTER=YUAN.MA



USB PORT B (BACK PORT)

R4652 1

J4600


2

SYM_VER-1

CRITICAL

C4695

2

5% 1/16W MF-LF 402

20% 16V CERM 402

C

CRITICAL

DLP0NS

9

R4690 IN

PP5V_S3_RTUSB_A_F


1

0.01uF


We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

64C6

C4605

GND TPAD 1

2

0603

EN2

USB_PWR_EN_R

C4690

OUT2

EN1

6

OC2*

4

NOSTUFF


MSOP

5

USB_EXTB_OC_L

1

PP5V_S3_RTUSB_A_ILIM

OC1*

3 20C2

OUT1

7

NC IO NC IO

8C3

20C2

2

NC IO NC IO

C

=PP5V_S3_EXTUSB

y r

a n i

Port Power Switch


2


5% 1/16W MF-LF 402


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 46

1

109

A

8

6

7

2

3

4

5

1

D

D

y r

38B4 8C3 =PP5V_S3_IR

1

C4801 0.1UF 10% 16V X7R-CERM 402

a n i

16

2

VDD 74B3 20D3

BI

74B3 20D3

BI

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_P

14

USB_IR_N

15

DIFFERENTIAL_PAIR=USB2_IR

IR_VREF_FILTER

18 20

1

23

C4803

24

1UF 2

10% 10V X5R 402-1

25 26

P1_0/D+ P1_1/DP1_2/VREG P1_3/SSEL P1_4/SCLK P1_5/SMOSI P1_6/MISO P1_7

P0_0 P0_1 P0_2/INT0 P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1 P0_7

7 6 5 4

R4800

3 2

1

IR_RX_OUT_RC

1

22

C

CY7C63833

P3_0 P3_1

QFN

P2_0 P2_1

1

9

2

P/N 338S0375

10

28 29

IR_RX_OUT

IN

7A7 38A4

C4804 0.001UF

8

CRITICAL OMIT 27

2

5% 1/16W MF-LF 402

32

U4800 21

100

10% 50V CERM 402

11

NC

NC

30

12 17

31

19

13

33

THRM_PAD VSS

m il

CYPRESS ’ENCORE II’ USB CONTROLLER

B

e r

CRITICAL

J4800

R4805

FF18-6A-R11AD-B-3H

1

F-RT-SM

10

2

1/16W

1 2

7A7 PP3V42_G3H_LIDSWITCH_R

1/16W

P 4

7A7

5

7A7

518S0692

1

2

A

=PP3V42_G3H_LIDSWITCH

10

=PP5V_S3_IR

2

402

SMC_LID_R SYS_LED_ANODE_R

1

C4806

1

C4807

1

100

1/16W

1

4.7

1

C4808

0.1UF

0.001UF

0.001UF

10% 16V X7R-CERM 402

10% 50V CERM 402

10% 50V CERM 402

2

8C3 38D7

SMC_LID 39B5 SYS_LED_ANODE 40A6

2

1/16W

PLACE PLACE PLACE PLACE

40C2 47A5

402 5% MF-LF

10% 16V X7R-CERM 402

2

2

R4808

402

5% MF-LF

0.1UF

2

8D1

R4807

5% MF-LF

C4805

B

PLACE R4805 NEAR J4800 PLACE R4806 NEAR J4800 PLACE R4807 NEAR J4800 PLACE R4808 NEAR J4800

R4806

1

PP5V_S3_IR_R

7A7

3

6

402

5% MF-LF

C

C4805 C4806 C4807 C4808

IR_RX_OUT

NEAR NEAR NEAR NEAR

7A7 38C4

J4800 J4800 J4800 J4800

Front Flex Support SYNC_MASTER=YUAN.MA



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 48

1

109

A

8

6

7

2

3

4

5

1

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

40B6 7C3 49D7 40D8 40C7 40C1 8D1

PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC

D

D C4902

1

1

2

2

22UF 20% 6.3V CERM 805

U4900

OUT

40D5

OUT

ESTARLDO_EN

D10

SMC_P24 SMC_P26

C

BI

74C3 41D5 19B3

BI

74C3 41D3 19B3

BI

74C3 41D3 19B3

BI

74C3 41D5 19C3

IN

26D1

IN

74C3 26C1 41D3 19B7

IN BI

LPC_AD LPC_AD LPC_AD LPC_AD LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ

49B7

BI OUT

OUT

48A6

OUT

41C5 40B2 39C5 37A8

OUT

B7 A8 D8 D7 D6

41C3 40B2 39C5 37A8 42D6

IN BI

D4 A5

(OC)

B4 A1

SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK

E10

C8

NC NC 40D5

E12

D9

40D5 42B5

F11

A9

NC SMC_P41 SMB_MGMT_DATA SMS_ONOFF_L

D12

F13

NC 74C3 41D5 19B3

E11

E13

NC 40D5

D13

C12

NC NC NC 40D5

C13

C2 B2 C1 C3 G2 F3

(OC)

E4

P20 P21 P22 P23 P24 P25 P26 P27

P70 P71 P72 P73 P74 P75 P76 P77

N10

L12

SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE

P30 P31 P32 P33 P34 P35 P36 P37

P80 P81 P82 P83 P84 P85 P86

A7

SMC_WAKE_SCI_L

P90 P91 P92 P93 P94 P95 P96 P97

J4

SMC_ADAPTER_EN

K13 J10

SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L

H12

M11 L10 N11 N12 M13 N13

B6

P40 P41 P42 P43 P44 P45 P46 P47

(OC)

PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMB_MGMT_CLK

(OC)

SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK SMB_0_S0_DATA

D5 A6 B5

26B3 37A6 29A5 28A5 21B3 21A4

B 56C2 40B2 23B5 21C7

SMC_PA0 SMC_PA1 PM_SYSRST_L OUT USB_DEBUGPRT_EN_L OUT MEM_EVENT_L BI 40A2 SMC_PA5 SYS_ONEWIRE BI PM_BATLOW_L OUT 40C2

N3 N1

(OC) (OC) (OC) (OC) (OC) (OC)

M3 M2 N2 L1 K3 L2 B8

NC

40A2

SMC_RUNTIME_SCI_L SMC_ODD_DETECT IN 40C5 SMC_PB3 (See below) SMC_EXCARD_CP IN

40B5

IN

40B2

IN

23C5 21C7

C9

OUT

36B7 7B7

B9 A10 C10 B10

NC

46B5

OUT

40D5

OUT

40D5

OUT

40D5

OUT

46C5

A

IN

40B2

IN

40B2

IN

40B2

IN

49B4

IN

49B4

IN

49B4

IN

40C5

IN

40D5

IN

40D5

IN

40D5

IN

40C5

IN

SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L

C11 A11

SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH

G11

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT ALS_RIGHT

M10

G13 F12 H13 G10 G12 H11 J13

N9 K10 L8 M9 N8 K9 L7

56B1

IN

44B1

IN

43D6

IN

40B2

IN

40D5

IN

44B1

IN

43B4

IN

44A4

IN

40B2

G3 H2 G1 H4 G4 F4 F1

PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

HS82117 LGA-HF

(2 OF 3) OMIT

PE0 PE1 PE2 PE3 PE4 PF0

K1

PF1 PF2 PF3 PF4 PF5 PF6 PF7

N5

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

M8

PH0 PH1 PH2 PH3 PH4 PH5

E2

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

19B7 41D5

OUT

37A8 39B8 40B2 41C5

IN

37A8 39B8 40B2 41C3

1

0.1UF 20% 10V CERM 402

AVCC

a n i 2

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

41C3 40D6

21C7 23C5

19C3 41D3

C4907

C4920

IN

42B5

SMC_RESET_L

D3

RES*

SMC_XTAL SMC_EXTAL

A3

XTAL EXTAL

A2

P

K2 J1 K4 K5

NC

SMC_SYS_LED SMC_LID

M6 L5 M5

NC NC

L4 M4

NC NC NC

N7 K8 K7 K6 N6 M7 L6

(OC) (OC) (OC) (OC) (OC) (OC)

F2 J2 A4 B3 C4

40B2 40D5 56C1

IN

7A7 40B2 56A8

IN

7C3 21C3 34B7 41A5 64D5 68D8

IN

7C3 21C3 40A2 64C8

IN

40A2

IN

26B1 74A3

40B2

IN

40B2 41C3

IN

40B2 41D3

OUT

40B2 41C5

IN

40B2 41D5

IN

VCC

1

0.47UF

10% 6.3V CERM-X5R 402

VCL AVREF

U4900

NC

HS82117

E5

2

R4909 1

NC

LGA-HF

(3 OF 3) OMIT

MD1 MD2

D1

NMI

E3

ETRST

H3

AVSS

L9

R4901 10K

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

SMC_MD1

IN

41C5

SMC_NMI

IN

41C3

SMC_TRST_L

IN

41C5

SMC_KBC_MDE

H1

1

VSS

XW4900 SM 2

1

10K

R4902

C

NO STUFF 1

1

R4998

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

R4903 0

5% 1/16W MF-LF 2 402

1

GND_SMC_AVSS

40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5

B

40A8

38B4 40C2 47A5

OUT

23B4

IN

40B5

BI

42C6

BI

42C6

BI

42D3

BI

42D3

BI

42C3

BI

NOTE: P94 and P95 are shorted, P95 could be spare.

42D6

IN

OUT

=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_PH2 ALS_GAIN

IN

BI

SMC_MCP_SAFE_MODE

N4

40A3 40C2 40C7 47C3

m il

e r J3

y r

PP3V3_S5_SMC_AVCC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

40A6

IN

BI

2

40A6

OUT

IN

P50 P51 P52

40C2

40D1

IN

OUT

U4900 (DEBUG_SW_1) (DEBUG_SW_2)

IN

4.7 5% 1/16W MF-LF 402

21C7 34B7 40B2

NC

C7

C6

OUT

NC

J11

SMC_VCL

R4999 1

L11

OUT

D11

J12

7C3 64D8

E1

60C7 23C5 21B7

OUT

K11

OUT

NC NC NC

H10

NC PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L

21B7

(1 OF 3) OMIT

K12

20% 10V CERM 402

M1

B13

L13

LGA-HF

2

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

SMC_PM_G2_EN

P60 P61 P62 P63 P64 P65 P66 P67

HS82117

0.1UF

20% 10V CERM 402

B1

A12

P10 P11 P12 P13 P14 P15 P16 P17

0.1UF 2

C5

IN

A13

20% 10V CERM 402

2

C4906

B11

IN

64B1

B12

0.1UF

20% 10V CERM 402

1

F10

64A4 26A8

SMC_EXCARD_PWR_EN SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD

C4905

1

M12

OUT

0.1UF

C4904

L3

OUT

1

D2

40D5 40C5

C4903

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

42C3

OUT

40C2

OUT

40C2

OUT

40C5

40B2

NC NC

SMC SYNC_MASTER=T18_MLB



SMC_PB3:


SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 49

1

109

A

8

6

7

2

3

4

5

1

SMC FSB to 3.3V Level Shifting 39A8

SMC_FAN_1_CTL

NC_SMC_FAN_1_CTL MAKE_BASE=TRUE

40A1 8B5 39A8

SMC_FAN_2_CTL

=PP3V3_S0_SMC

NC_SMC_FAN_2_CTL MAKE_BASE=TRUE

39A8

SMC_FAN_3_CTL

39B8

SMC_GFX_THROTTLE_L

1

NC_SMC_FAN_3_CTL

R5060

MAKE_BASE=TRUE

SMC Reset "Button" / Brownout Detect

470 SMC_IG_THROTTLE_L

21A4 21B3

8D7

=PP1V05_S0_SMC_LS

5%

MAKE_BASE=TRUE

1/16W MF-LF

39C8

ESTARLDO_EN

NC_ESTARLDO_EN

49D7 40C7 40C1 39D4 8D1 =PP3V3_S5_SMC

1

MAKE_BASE=TRUE

56C1 40B2 39C5

SMC_BC_ACOK

=CHGR_ACOK

D

C5000

1

0.1uF 20% 10V CERM 402

U5000

2

NCP303LSN SOT23-5-HF 5

SMC_MANUAL_RST_L NOSTUFF 1

2

OUT IN

CD NC GND

C5001

0 SILK_PART=SMC_RST

4

NC

R5001

1

2

SMC_P24

39C8

SMC_P26

1

39C8

SMC_P41

39A8

SMC_NB_CORE_ISENSE

44A5

TO CPU

SMC_MCP_CORE_ISENSE

2

39A8

SMC_NB_DDR_ISENSE

39A8

ALS_LEFT

SMC_MCP_DDR_ISENSE

BI

CPU_PROCHOT_L

1

5% 1/16W

2

Q5032

D

402

6

SMC_MCP_VSENSE

39C5

SMC_GPU_VSENSE

39D8

SMC_EXCARD_PWR_EN

39D8

SMC_RSTGATE_L

39B8

SMC_PB3

43D6

MAKE_BASE=TRUE

3

SSM6N15FEAPE

SSM6N15FEAPE

TP_SMC_EXCARD_PWR_EN

SOT563

TP_SMC_RSTGATE_L MAKE_BASE=TRUE

5

5 47B1 SMC_TPAD_RST_L

1

SMC_ONOFF_L

2

S

39A5

ALS_GAIN

39A8

SMC_ANALOG_ID

1

39A8

ALS_RIGHT

MAKE_BASE=TRUE

NC_SMC_ANALOG_ID MAKE_BASE=TRUE

SOT553-5

SMC_TPAD_RST

G

2

SMC_PROCHOT

NC_ALS_GAIN

U5001

S

a n i

NC_SMC_PB3 MAKE_BASE=TRUE

4

SN74LVC1G02 4

47C3 40C2 40A3 39C5

G

Q5059

MAKE_BASE=TRUE

SOT563

49D7 40D8 40C1 39D4 8D1 =PP3V3_S5_SMC

D

71B3 14B7 10C6

NC_ALS_RIGHT MAKE_BASE=TRUE

02

OUT

PM_THRMTRIP_L

3

D

Q5059

SSM6N15FEAPE

3

SOT563

4

S

G

5

IN

SMC_THRMTRIP

C

SMC AVREF Supply

m il

CRITICAL

VR5020 8D1

R5095

REF3333

=PPVIN_S5_SMCVREF

PP3V3_S5_AVREF_SMC

SOT23-3

1

IN

OUT

0

7C3 39D4 39B8


2

OUT

SMC_EXCARD_OC_L

1

C5026 0.01UF

2 1

2

C5020 0.47UF

10uF

10% 6.3V CERM-X5R 402

20% 6.3V X5R 603

39B5

10% 16V CERM 402

353S1381

353S1278

BOM OPTION

REF DES

COMMENTS:

ALL

Intersil ISL60002-33

e r

39C2 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5


TABLE_ALT_ITEM

B System (Sleep) LED Circuit 8C3

=PP5V_S3_SYSLED

R5031

1

1

523 1% 1/16W MF-LF 402

R5030 20

2

2

1% 1/16W MF-LF 402

SYS_LED_ILIM 2 SOD

R5032

P

2SA2154MFV-YAE

SYS_LED_L_VDIV

Q5030

1

1

3

1.47K

SYS_LED_ANODE

1% 1/16W MF-LF 402 2

SYS_LED_L

A Q5032

D

6

SSM6N15FEAPE

=SMC_SMS_INT

2

TABLE_ALT_HEAD

ALTERNATE FOR PART NUMBER

EXCARD_OC_L

SMS_INT_L

MAKE_BASE=TRUE

GND_SMC_AVSS

PART NUMBER

OUT

1

C5025

2

5% 1/16W MF-LF 402

GND 3

1

OUT

SMC Crystal Circuit

39C3

39A5

39B8

SMC_PA0

39B8

SMC_PA1

R5091 R5092

IN

100K

1

2

100K

1

2

1

2

SMC_LID

R5070 R5071

10K

47A5 39B5 38B4

100K

1

2

39A5

SMC_PH2

R5072

10K

1

2

SMC_ONOFF_L

41C5 39C5 39B8 37A8

R5073 R5074

SMC_TX_L SMC_RX_L

10K

1

100K

=PP3V3_S5_SMC

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

2

1

2

ONEWIRE_PU

49C7

56C2 39B8

56A8 39C5 7A7 41D5 39B5

2.0K

1

2

SMC_BS_ALRT_L

R5075 R5076

100K

1

2

SMC_TMS

R5077

10K

1

2

SYS_ONEWIRE

41D3 39B5

SMC_TDI

R5078 R5079

41C3 39B5

SMC_TCK

R5080

10K

1

2

SMC_BC_ACOK

R5087 R5050

470K

1

2

41C5 39B5

56C1 40D5 39C5 39A8

SMC_TDO

SMC_GFX_OVERTEMP_L

10K 10K

1

2

1

10K

2

1

2

B 39A8

SMC_FAN_1_TACH

R5051

10K

1

2

39A8

SMC_FAN_2_TACH

1

2

SMC_FAN_3_TACH

R5052 R5053

10K

39A8

10K

1

2

39C5

SMC_GPU_ISENSE

R5054

10K

1

2

39C5

SMC_NB_MISC_ISENSE

R5055

10K

1

2

39D5 34B7 21C7

Debug Power "Button"

39B5

39B8

R5085 R5086

SMC_ADAPTER_EN SMC_CASE_OPEN

R5088

SMC_EXCARD_CP

10K

1

2

10K

1

2

10K

1

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

2

15pF 1

1

20.00MHZ 2

C5011 15pF 1

OUT

NOSTUFF 1

SILK_PART=PWR_BTN

5X3.2-SM

SMC_EXTAL

SMC_ONOFF_L

5% 50V CERM 402

CRITICAL

Y5010

2

2

R5015

39C5

NOSTUFF 1

R5016

0

0

5% 1/10W MF-LF 603

5% 1/10W MF-LF 603

2

39C5 40C2 40C7 47C3

2

64C8 39C5 21C3 7C3

R5090

PM_SLP_S5_L

100K

1

2

PM_SLP_S4_L

PLACE R5015,R5001 ON BOTTOM SIDE PLACE R5016 ON TOP SIDE

SILK_PART=PWR_BTN 39B8

R5089

SMC_PA5

10K

1

2

5%

5% 50V CERM 402

38B4

=PP3V3_S0_SMC

40D2 8B5

1/16W

MF-LF

402

SMC Support SYNC_MASTER=YUAN.MA



SOT563 39B5

C 49D7 40D8 40C7 39D4 8D1

41C3 39C5 39B8 37A8

IN

39A5

20C2

C5010

SMC_XTAL

39C3

IN

47C3 40C7 40A3 39C5

IN

4

BC847BV-X-F SOT563-HF

1

MF-LF

44B5

BC847BV-X-F SOT563-HF

Q5060

2

CPU_PROCHOT_L_R

2

44C5

SMC_CPU_FSB_ISENSE MAKE_BASE=TRUE

10% 16V CERM 402

y r

3.3K 71B3 60C8 14B6 10C5

MAKE_BASE=TRUE

3

Q5060 5

6

R5062

44D5

MAKE_BASE=TRUE

39C3 41C3

3

402

CPU_PROCHOT_BUF

TP_SMC_P41

0.01UF

5% 1/10W MF-LF 603

2

SMC_BMON_MUX_SEL MAKE_BASE=TRUE

OUT

D

MF-LF

MAKE_BASE=TRUE

SMC_RESET_L

39C5

1/16W

TP_SMC_P24 MAKE_BASE=TRUE

5% 1/16W MF-LF 402

OUT

5%

R5000 1K

CRITICAL

39C8

SMC_PROCHOT_3_3_L

3.3K

57B5

MAKE_BASE=TRUE 1

R5061

TO SMC

402

2

SMC_SYS_LED

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 2

G

S


1


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 50

1

109

A

8

6

7

2

3

4

5

1

LPC+SPI Connector CRITICAL LPCPLUS

J5100

55909-0374

D

41C7 41C3 41B7 8D1 8D5

74C3 39C8 19B3

BI

74C3 39C8 19B3

BI

74A3 41C5 74A3 41B5 74C3 39C8 19C3 39C5 19B7 40B2 39B5

39C1 40B2 39C5 39B8 37A8

41D5 41C3 41B7 8D1

=PP3V3_S5_LPCPLUS 1

C

74A3 41A5 21B3

IN

IN OUT IN

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

33

34

D LPC_CLK33M_LPCPLUS LPC_AD LPC_AD SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

VCC 1 Y+ 2 Y-

SPI_MOSI_R

U5110

M+ 5 M- 4

SPI_ALT_CLK SPI_ALT_MOSI

OUT

41D3 74A3

R51911 10K

OUT

41D5 74A3

SPI_CLK_MUX SPI_MOSI_MUX

OUT

41A8 50C6

CRITICAL SPIROM_USE_MLB

10 SEL

OUT

41A8 50C3

3

m il

LPCPLUS

=PP3V3_S5_LPCPLUS

C5124 20% 10V 402

9

2 CERM

SPI_ALT_MISO

IN

VCC

IN

SPI_MISO SPI_CS0_R_L

1 Y+ 2 Y-

U5120

M+ 5 M- 4

1/16W

D+ 7 D- 6 SPI_MLB_CS_L_MUX

OE* 8 GND

20K

5% 1/16W MF-LF 402 2

R5146 0

1

2

5% PLACEMENT_NOTE=PLACE NEXT TO U1400 1/16W MF-LF 402

P

SPI MUX BYPASS LPCPLUS_NOT R5156 50C6 41C5

OUT

SPI_CLK_MUX

1

0

2

5% 1/16W MF-LF 402 50C3 41C5

OUT

LPCPLUS_NOT R5157 0

SPI_MOSI_MUX

1

LPCPLUS_NOT R5158 50C3 41B5

IN

0

SPI_MISO_MUX

1

2 5% 1/16W MF-LF 402

A

2

IN

SPI_CLK_R

SPI_MOSI_R

IN

OUT

19C3 39C5 39B5 40B2 39B5 40B2

OUT

39C3 40D6

OUT

39C1

OUT

37A8 39B8 39C5 40B2

OUT

18B7

=PP3V3_S0_LPCPLUS =PP3V3_S5_LPCPLUS

R5147 0

R5140 1 100K 5% 1/16W MF-LF 402

21B3 41C7 74A3

OUT

21B3 41B7 74A3

C

MCP_CS1_YES 2

3

LPC_FRAME_PU

MCP_CS1_YES R5141 1

2

1

Q5140

470 5% 1/16W MF-LF 402 2

SSM3J16FV SOD-VESM-HF

MCP_CS1_NO

LPC_FRAME_R_L

R5142 1

0

OUT

19C5

2

5% PLACEMENT_NOTE=Place near J5100 1/16W MF-LF 402

74A3

SPI_CS1_R_L_USE_MLB

=SPI_CS1_R_L_USE_MLB

BI

MAKE_BASE=TRUE

21C7

To Frank Card

2

PLACEMENT_NOTE=PLACE NEXT TO U5120

8A3 41C7 50C6

B

SPI Frequency Clamp

ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER. NO STUFF Keep very short

R5161

MCP_FORCE_SPI_DO_L 23C4 8A3

=PP3V3_S5_MCP_A01 MCP_A01&MCP_A01Q

R51631

MCP_A01&MCP_A01Q

Q5160

SPI_MOSI

2

SPI_CLK

OUT

50C4 74A3

OUT

50C5 74A3

MCP_A01&MCP_A01Q

SOT563

R5162

5% 1/16W MF-LF 402 2

2

G

1

S 1

0

2

5% 1/16W MF-LF 402

MCP_SPI_FORCE MCP_A01&MCP_A01Q

Q5160

0

1

5% 1/16W MF-LF 402

D 6

SSM6N15FEAPE

100K

21B3 41C8 74A3

IN

NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON

50C6

=PP3V3_S5_ROM

D 3

SLP_S3# nVidia recommendation, SSM6N15FEAPE SOT563 not compatible with button-mashing. MCP_A01&MCP_A01Q

5% 1/16W MF-LF 402

SPI_MISO

MCP_CS1_YES

5% 1/16W MF-LF 402

41A8 50C3

MCP_CS1_NO 0 2 R5126 SPI_MLB_CS_L 1 1/16W 402 5% MCP_CS1_NO MF-LF

R5144

MCP_CS1_YES&LPCPLUS_NOT

41D3

1

SPI_MISO_MUX

1

3

B

5% MF-LF

OUT

402

e r

CRITICAL 10 SEL

41D5 74A3

MCP_CS1_NO Pull-up on debug card 0 2 R5127 SPI_ALT_CS_L

1 SPI_ALT_CS_L_MUX

PI3USB102ZLE TQFN

y r

19B7 39C8

IN OUT OUT

From Frank Card

0.1UF

OUT

41B5

BI

G

SPIROM_USE_MLB

41D3 41C7

1

74A3 21B3

IN

MCP SPI Override Options

SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)

74A3 41A5 21B3

41C5 74A3

MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX

OE* 8

LPCPLUS

41C5 41C7

IN

41D5 41C7 41B7 8D1

GND

41D5 41C7 41C3 8D1

OUT

D

41D3 41C5

19B3 39C8 74C3

S

5% 1/16W MF-LF 402 2

D+ 7 D- 6

19B3 39C8 74C3

BI

8C5

PI3USB102ZLE TQFN

BI

MCP79 Internal SPI MUX Support

516S0573

20% 10V 402

26B1 74C3

IN

a n i

C5114

2 CERM

9

LPCPLUS

5% 1/16W MF-LF 402 2

SPI_CLK_R

OUT

0.1UF

10K

IN

IN OUT

1

LPCPLUS

=PP3V3_S5_ROM

R51901

74A3 41A5 21B3

SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L

IN OUT

OUT 39C1

MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP

50C6 41B5 8A3

LPC_AD LPC_AD

IN

Alternate SPI ROM Support

M-ST-SM 31 32

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS

R5160 68D8 64D5 39C5 34B7 21C3 7C3

IN

PM_SLP_S3_L

0

1

2

5

G

S 4

LPC+SPI Debug Connector

MCP_SPI_FORCE_L

5% 1/16W MF-LF 402

SYNC_MASTER=CHANGZHANG



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 51

1

109

A

8

6

7

MCP79 SMBUS "0" CONNECTIONS

2

3

4

5

SMC "0" SMBus Connections

1

SMC "A" SMBus Connections NOTE: SMC RMT bus remains powered and may be active in S3 state

8C5

=PP3V3_S0_SMBUS_MCP_0

8C5

R5200

MCP79 U1400 (MASTER)

D

21C3 13B6 74B3 21C3 13B6 74B3

1

1

R5201

4.7K

4.7K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

2

SMBUS_MCP_0_CLK

SO-DIMM "A"

SMC

J3100 (Write: 0xA0 Read: 0xA1)

U4900 (MASTER)

=PP3V3_S0_SMBUS_SMC_0_S0

8D3

R5250

=I2C_SODIMMA_SCL

28A5

39B8

SMB_0_S0_CLK

76D3

=I2C_SODIMMA_SDA

28A5

39B5

SMB_0_S0_DATA

76D3

MAKE_BASE=TRUE

1

1

R5251

4.7K

4.7K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

2

SMBUS_SMC_0_S0_SCL

R5270 1

MCP Temp

SMC

EMC1403-5: U5535 (Write: 0x98 Read: 0x99)

U4900 (MASTER)

MAKE_BASE=TRUE

5% 1/16W MF-LF 402

=I2C_MCPTHMSNS_SCL

45B3

39A5

SMB_A_S3_CLK

76D3 7D5 7B5

=I2C_MCPTHMSNS_SDA

45B3

39A5

SMB_A_S3_DATA

76D3 7C5 7B5

29A5

a n i

=PP3V42_G3H_SMBUS_SMC_BSA

8A3

39A5

=PP3V3_S5_SMBUS_MCP_1 NOSTUFF 1

R5232

MCP79 U1400 (MASTER?) 74B3 21C3

SMBUS_MCP_1_CLK

74B3 21C3

SMBUS_MCP_1_DATA

R5230

1

2.0K 5% 1/16W MF-LF 402 2

1

R5231 2.0K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 402

SMB_BSA_CLK

76D3 7A7

SMB_BSA_DATA

76D3

NOSTUFF 1

R5233

10K

10K

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

1K

2

2

BATTERY & BIL

SMC

J6950 & J6955 (See Table)

U4900 (MASTER)

5% 1/16W MF-LF 402

SMBUS_SMC_BSA_SCL

=SMBUS_BATT_SCL

SMBUS_SMC_BSA_SDA

=SMBUS_BATT_SDA

MAKE_BASE=TRUE

HDCP ROM U2690 OR U2695 (Write: 0xA0-0xAE, Read: 0xA1-0xAF) (All 8 addresses used)

J5800 (Write: 0x90 Read: 0x91)

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

=I2C_TPAD_SCL

48C1

=I2C_TPAD_SDA

48C1

D

ALS J3401 (Write: 0x52 Read: 0x53) I2C_ALS_SCL

31B6

I2C_ALS_SDA

31B6

56A3 56A6

56A3 56A6

39A5

39A5

SMB_B_S0_CLK

SMB_B_S0_DATA

=PP3V3_S0_SMBUS_SMC_B_S0

R5260 1

76D3

1

R5261

4.7K

4.7K

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

2

2

CPU Temp EMC1403-5: U5515 (Write: 0x98 Read: 0x99)

SMBUS_SMC_B_S0_SCL

=I2C_CPUTHMSNS_SCL

45D3

=I2C_CPUTHMSNS_SDA

45D3

C

MAKE_BASE=TRUE

76D3

SMBUS_SMC_B_S0_SDA MAKE_BASE=TRUE

Battery Charger

ISL6258A - U7000 (Write: 0x12 Read: 0x13)

Battery

=I2C_HDCPROM_SCL

25A6

=I2C_HDCPROM_SDA

25A6

MAKE_BASE=TRUE MAKE_BASE=TRUE

m il

Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)

Mikey U6860 (WRITE: 0X72 READ: 0X73)

=I2C_MIKEY_SCL

52C7

=I2C_MIKEY_SDA

52C7

=SMBUS_CHGR_SCL

57C6

=SMBUS_CHGR_SDA

57C6

SMC "Management" SMBus Connections

The bus formerly known as "Battery B"

8D3

e r SMC

U4900 (MASTER)

B

39C5

39C8

P

A

R5281

MAKE_BASE=TRUE 39A5

=PP3V3_S0_SMBUS_MCP_1

1

1K

U4900 (MASTER)

MCP79 SMBUS "1" CONNECTIONS C

8C5

R5280 1

SMC

2

5% 1/16W MF-LF 402

SMC "B" SMBus Connections

SMC "Battery A" SMBus Connections 8D1

2

y r

SO-DIMM "B"

29A5

TRACKPAD

1K

MAKE_BASE=TRUE

J3200 (Write: 0xA2 Read: 0xA3)

=I2C_SODIMMB_SDA

R5271

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA MAKE_BASE=TRUE

=I2C_SODIMMB_SCL

1

1K

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

8B5

=PP3V3_S3_SMBUS_SMC_A_S3

SMB_MGMT_CLK

SMB_MGMT_DATA

=PP3V3_S3_SMBUS_SMC_MGMT

R5290 1 4.7K

5% 1/16W MF-LF 402 2

76D3

1

R5291 4.7K

Vref DACs

U2900 (Write: 0x98 Read: 0x99)

5% 1/16W MF-LF 2 402

SMBUS_SMC_MGMT_SCL

=I2C_VREFDACS_SCL

27C7

=I2C_VREFDACS_SDA

27C7

B

MAKE_BASE=TRUE

76D3

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

Margin Control U2901 (Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

27A8

=I2C_PCA9557D_SDA

27A8

SMS U5930 (Write: 0x70 Read: 0x71) =I2C_SMS_SCL

49C6

=I2C_SMS_SDA

49C6

M97 SMBUS CONNECTIONS SYNC_MASTER=BEN



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 52

1

109

A

8

6

7

2

3

4

5

1

CPU Voltage Sense / Filter 8D7

=PPVCORE_S0_CPU_VSENSE

XW5309

R5309

SM 1

2

4.53K

CPUVSENSE_IN

1

SMC_CPU_VSENSE

2

PLACEMENT_NOTE=Place near U1000 center

1% 1/16W MF-LF 402

1

39C5

0.22UF 2

D

OUT

C5309 20% 6.3V X5R 402

GND_SMC_AVSS

D

39C2 40B6 43B5 43C6 44A1 44A4 44B2 44B5 44C5 44D5

Place RC close to SMC

y r

MCP Voltage Sense / Filter 8C7

=PPVCORE_S0_MCP_VSENSE

XW5359

R5359

SM 1

2

MCPVSENSE_IN

1

4.53K

PLACEMENT_NOTE=Place near U1400 center

1% 1/16W MF-LF 402

SMC_MCP_VSENSE

2

1

OUT

40D4

C5359 0.22UF

2

20% 6.3V X5R 402

GND_SMC_AVSS

a n i

39C2 40B6 43B5 43D6 44A1 44A4 44B2 44B5 44C5 44D5


C PBUS VOLTAGE SENSE ENABLE & FILTER

m il

Q5315 NTUD3127CXXG SOT-963

N-CHANNEL

6

PBUSVSENS_EN_L

D

R5316 1 64C1

IN

=PBUSVSENS_EN

2

100K

G

1% 1/16W MF-LF 402

S

Enables PBUS VSense divider when high.

1 3

5 8C1

PPBUS_G3HRS5_VSENSE

e r 1% 1/16W MF-LF 402

4

P-CHANNEL

B

R53151 100K 1% 1/16W MF-LF 402

R5385 1 27.4K

G S

=PPBUS_G3HRS5

2


D

R5386

2

1

5.49K 1% 1/16W MF-LF 402

2

PBUSVSENS_EN_L_DIV

P

A

2

C

RTHEVENIN = 4573 OHMS SMC_PBUS_VSENSE

1

OUT

39C5

B

C5385 0.22UF

2

20% 6.3V X5R 402

GND_SMC_AVSS

39C2 40B6 43C6 43D6 44A1 44A4 44B2 44B5 44C5 44D5


VOLTAGE SENSING SYNC_MASTER=YUNWU



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 53

1

109

A

8

6

7

2

3

4

5

1

MCP VCore Current Sense

8B5

=PP5VR3V3_S0_MCPCOREISNS 1

R5490

C5415 0.1uF

0.001

8C8

2 10V CERM

61C4 77D3

77D3

U5400

8C8 22D5 24D8 61B1

OUT

MCP VCore Current Sense Filter

V+

402

2 =PPVCORE_S0_MCP 4

1 IN =PPVCORE_S0_MCP_REG_R 3

D

3

20%

1% 1W MF 1206

ISNS_PVCORES0MCP_N

5 IN-

ISNS_PVCORES0MCP_P

4 IN+

R5416

INA213 SC70

6

OUT

1

MCPCORE_IOUT

4.53K

2

SMC_MCP_CORE_ISENSE

1% 1/16W MF-LF 402

REF 1

OUT

D

40D4

y r

C5472

1

0.22UF

GND

20% 6.3V X5R 402

2

2

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44C5


MCP MEM VDD Current Sense 8B5

1

C5416

1 3

=PP1V5_S0_FET_R

3

20% 10V

1% 1/4W MF 1206

IN

MCP MEM VDD Current Sense Filter

0.1uF

0.002

8B8

2 CERM

V+

402

2 =PP1V5_S0 4 77D3

77D3

a n i

=PP3V3_S0_MCPDDRISNS

R5491

OUT

U5401

8B8

5 IN-

ISNS_P1V5S0MCP_N

OUT 6

SC70

4 IN+

ISNS_P1V5S0MCP_P

R5417

INA210

C

MCPDDR_IOUT

1

4.53K

SMC_MCP_DDR_ISENSE

2

1% 1/16W MF-LF 402

REF 1

OUT

40D4

C5435

1

0.22UF

GND

20% 6.3V X5R 402

2

2

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44B5 44D5


m il

CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE 8B5

=PP3V3_S0_CPUVTTISNS 1

R5492

C5417 0.1uF

0.01

8C1

IN

=PPCPUVCORE_VTT_ISNS_R 1 3

3

20%

0.5% 1W MF 0612

2 10V CERM

V+

402

2 =PPCPUVCORE_VTT_ISNS OUT 4

U5402

8C2

77D3

ISNS_CPUVTT_N

5 IN-

77D3

ISNS_CPUVTT_P

4 IN+

R5418

INA213 SC70

OUT 6

CPUVTT_IOUT

1

4.53K

2

SMC_CPU_FSB_ISENSE

1% 1/16W MF-LF 402

REF 1

1

C5436

e r

GND

0.22UF 20% 6.3V X5R 402

2

2

GND_SMC_AVSS

B


BMON CURRENT SENSE

P

OUT

CPU VCore Load Side Current Sense / Filter 60C7

=PP3V42_G3H_BMON_ISNS

ENG_BMON 1

C5418

BMON_INA_OUT

0.1uF 3

20% 10V

2 CERM

REGULATOR SIDE

402

V+

ENG_BMON

U5403 77D3 57B3

77D3 57B3

OUT

IN

CHGR_CSO_R_P CHGR_CSO_R_N LOAD SIDE

SC70

4 IN+

OUT

6

REF 1

GND 2

A

5 IN-

INA213

NOTE: MONITORING CURRENT FROM BATTERY TO PBUS (BATTERY DISCHARGE) ACROSS R7008

57B5

IN

IMVP6_IMON


R5471 6.19K 1

SMC_CPU_ISENSE

2

OUT

39C5

1% 1/16W

R5480

MF-LF 402

1

1

0.22UF

17.4K 1% 1/16W MF-LF 402

C5470 20% 6.3V

2

X5R 402

2

GND_SMC_AVSS

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B5 44C5 44D5

39C2 40B6 43B5 43C6 43D6 44A1 44A4 44B2 44C5 44D5

B DC-IN (AMON) CURRENT SENSE R5481 IN

CHGR_AMON

1

4.53K 1% 1/16W MF-LF 402

ENG_BMON 1

2

SMC_DCIN_ISENSE 1

39C5

0.22UF 2

C5459

OUT

C5487 20% 6.3V X5R 402

0.1uF

U5413

NC7SB3157P6XG SC70 1 B1 SEL 6

IN

40D4

PLACE U5413, R5423, R5431, C5459 NEAR SMC (U4900)

8D1

C

GND_SMC_AVSS

20% 10V

39C2 40B6 43B5 43C6 43D6 44A4 44B2 44B5 44C5 44D5

2 CERM

SMC_BMON_MUX_SEL

IN

402

40D4

1

2 GND

VCC 5

R5401

0

3

CHGR_BMON

4 B0 ENG_BMON

BMON_AMUX_OUT

1

4.53K

2

SMC_BATT_ISENSE

A

VER 1

1 ENG_BMON

PROD_BMON

R5423

R5431

1% 1/16W MF-LF 402

1

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

39C5

C5490

Current Sensing

0.22UF

100K

0

OUT

2

20% 6.3V X5R 402

GND_SMC_AVSS

SYNC_MASTER=YUNWU


NOTICE OF PROPRIETARY PROPERTY 39C2 40B6 43B5 43C6 43D6 44A1 44B2 44B5 44C5 44D5


PLACE R5491 AND C5390 CLOSE TO SMC


INA213 has gain of 50V/V

For engineering, stuff U5313 and unstuff R5330 For production, stuff R5330 and unstuff U5313

PLACE U5403 AND C5418 NEAR R7008

SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 54

1

109

A

8

6

7

2

3

4

5

1

CPU T-Diode Thermal Sensor INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE 8B5

R5515

=PP3V3_S0_CPUTHMSNS

47

1

PP3V3_S0_CPUTHMSNS_R

2


5% 1/16W MF-LF 402

D

1 1

VDD 77D3 10C6

CPU_THERMD_P

BI

U5515

C5521

10K

2

2

5% 1/16W MF-LF 402

CPUTHMSNS_THERM_L

ALERT*

8

CPUTHMSNS_ALERT_L

SMDATA

9

=I2C_CPUTHMSNS_SDA

BI

42C1

10

=I2C_CPUTHMSNS_SCL

BI

42C1

THERM*

3

DN1

4

DP2

5

DN2

D

R5517

7

DP1

y r

2

CPU_THERMD_N

BI

2

TSSOP

2

1

10K 5% 1/16W MF-LF 402

20% 10V CERM 402

0.0022uF 10% 50V CERM 402

77D3 10C6

1

R5516 1

0.1uF

EMC1403-1-AIZL

SIGNAL_MODOL=EMPTY

DETECT CPU DIE TEMPERATURE

C5515

CRITICAL

SMCLK

GND 6

77D3

SIGNAL_MODOL=EMPTY 1

Q5501

DETECT FIN-STACK TEMPERATURE

a n i

CPUTHMSNS_D2_P

3

PLACEMENT NOTE: PLACE U5515 NEAR CPU

C5520

1

0.0022uF

BC846BMXXH

10% 50V CERM 402

SOT732-3 2 77D3

2

CPUTHMSNS_D2_N

MCP T-Diode Thermal Sensor

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

C

8B5

R5535

=PP3V3_S0_MCPTHMSNS

1

47

PP3V3_S0_MCPTHMSNS_R

2


5% 1/16W MF-LF 402

1 1

VDD 77D3 21C3

BI

MCP_THMDIODE_P

C5522

77D3 21C3

BI

1

2

EMC1403-1-AIZL TSSOP

10% 50V CERM 402

77D3 7C7

3

5% 1/16W MF-LF 2 402

THERM*

7

MCPTHMSNS_THERM_L

DN1

ALERT*

8

MCPTHMSNS_ALERT_L

4

DP2

SMDATA

9

=I2C_MCPTHMSNS_SDA

BI

42D3

5

DN2

10

=I2C_MCPTHMSNS_SCL

BI

42D3

2

CRITICAL

SMCLK

MCPTHMSNS_D2_P

SIGNAL_MODOL=EMPTY

DETECT HEAT-PIPE TEMPERATURE

C5540

1

1

PLACEMENT NOTE: PLACE U5535 NEAR MCP

0.0022uF

2

10% 50V CERM 402

e r

4

77D3 7C7

B

REPLACED 518S0521 WITH 518S0519

P

A

10K

DP1

6

J5590

R5537

5% 1/16W MF-LF 402 2

3

GND

78171-0002

1

10K

2

0.0022uF

MCP_THMDIODE_N

CRITICAL

M-RT-SM

20% 10V CERM 402

m il

DETECT MCP DIE TEMPERATURE

R5536 1

0.1uF

U5535

SIGNAL_MODOL=EMPTY

C5535

C

2

MCPTHMSNS_D2_N

B

Thermal Sensors SYNC_MASTER=YUNWU



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 55

1

109

A

8

7

6

2

3

4

5

1

D

D

8D5

8C5

y r

a n i

=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT

CRITICAL

R5660 1

C

47K 5%

R5665 39A8

1/16W MF-LF 402

7D7

5% 1/16W MF-LF 402

m il R5661 1

39A8

1

Q5660

1 2 3 4

NC

C

5V DC TACH MOTOR CONTROL GND

6

518S0521

7D7

FAN_RT_PWM

3

D

SOD-VESM-HF

2

SMC_FAN_0_CTL

2

SSM3K15FV

G

2

S

1/16W MF-LF 402

78171-0004 M-RT-SM NC 5

147K2 FAN_RT_TACH

SMC_FAN_0_TACH

100K 5%

J5601

e r

B

P

A

B

Fan SYNC_MASTER=CHANGZHANG



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 56

1

109

A

8

6

7

2

3

4

5

1

KEYBOARD CONNECTOR IC

PIN NAME

CURRENT

R_SNS

V_SNS

POWER

10UA

2.55 KOHM

0.0255 V

0.255E-6 W

0.204 V

16.32E-6 W

V+

3V3 LDO

VDD

60MA MAX

10 OHM

VOUT

60MA MAX

0.2 OHM

0.012 V

1.5 OHM

0.012 V

96E-6 W

0.021 V

294E-6 W

80UA

USB INTERFACES TO MLB SPI HOST TO Z2

TRACKPAD PICK BUTTONS KEYBOARD SCANNER

D

PSOC

VDD

18V BOOSTER

VIN

8MA (TYP)

0.6 V

14MA (MAX)

PP3V3_S3_PSOC

48C1 7B5 48C3 7B5

48C3 7C5 48C1 7B5 48C1 7B5 48C1 7B5 48C1 7B5 48C1 7B5 48C3 7C5 48C3 7C5 48C3 7C5 48C3 7C5

4MA (MAX)

4.7 OHM

0.0188 V

75.2E-6 W

45

43

44

46

47

48

49

51

52

50

54

TPAD_DEBUG

CRITICAL

U5701 CY8C24794 MLF

(SYM-VER2) APN 337S2983 OMIT

TEST POINTS ARE FOR ON BOARD PROGRAMMING

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD

42

WS_KBD17 7A5 47C2 WS_KBD16N 47C3 WS_KBD15_C 47C3 WS_KBD14 7A5 47C2 WS_KBD13 7A5 47C2 WS_KBD12 7A5 47C2 WS_KBD11 7A5 47C2 WS_KBD10 7A5 47D2 WS_KBD9 7A5 47D2 WS_KBD8 7A5 47D2 WS_KBD7 7B5 47D2 WS_KBD1 7B5 47D2 WS_KBD2 7B5 47D2 WS_KBD3 7B5 47D2

41 40 39 38 37 36 35 34 33 32 31 30 29

J5702

R5714

FH19C-4S-0.5SH25

470

47C6

F-RT-SM1

NC 47D2 47B5 47A6 8C3

2 47B8

3

ISSP_SCLK_P1_1

ISSP CLOCK

4 47C6

47C6

6

APN 518S0430

40C7 40C2 40A3 39C5

57

1

2

OUT

SMC_ONOFF_L

2

WS_KBD4 WS_KBD5 WS_KBD6 ISSP_SDATA_P1_0

29

C5725

7B5 47D2

0.1UF

7B5 47D2

m il =PP3V42_G3H_TPAD

47C6

47D2 47C5 47B5 47A6 8C3

Z2_CLKIN

=PP3V3_S3_TPAD

5

2

TC7SZ08AFEAPE SOT665

A

47C2 47B3 7A5

1

WS_LEFT_SHIFT_KBD

1

WS_LEFT_SHIFT_KEY 47D8

4

U5725 Y

7B5 48C3

2

20% 10V CERM 402

CRITICAL

B

3

TP_P7_7

ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL

20% 10V CERM 402

28

y r

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4

C5726

C

3 2 1

NC

PLACEMENT_NOTE=NEAR J5713

7B5 47D2

ISSP SDATA/I2C SDA TP_PSOC_P1_3

C5710 0.1UF

47C2 47B5 47B3 8D1

47C6

WS_KBD16N

1% 1/16W MF-LF 402

ISOLATION CIRCUIT TP_PSOC_SDA

10K

1

TP_PSOC_SCL

2

R5715

ISSP DATA

ISSP_SDATA_P1_0

NC

1

1% 1/16W MF-LF 402

1

=PP3V3_S3_TPAD

WS_KBD15_C

a n i

5

D

30

WS_KBD1 47C6 7B5 WS_KBD2 47C6 7B5 WS_KBD3 WS_KBD4 47C6 7B5 47C6 7B5 WS_KBD5 47C6 7B5 WS_KBD6 47C6 7B5 WS_KBD7 47C6 7A5 WS_KBD8 47C6 7A5 WS_KBD9 47C6 7A5 WS_KBD10 47C6 7A5 WS_KBD11 47C6 7A5 WS_KBD12 47C6 7A5 WS_KBD13 47C6 7A5 WS_KBD14 7A5 WS_KBD15_CAP 7A5 WS_KBD16_NUM 47C6 7A5 WS_KBD17 47D7 7A5 WS_KBD18 47D7 7A5 WS_KBD19 47D7 7A5 WS_KBD20 47D7 7A5 WS_KBD21 47D7 7A5 WS_KBD22 R5710 47D7 7A5 WS_KBD23 1K 1 2 7A5 WS_KBD_ONOFF_L 5% 47C5 47B5 47B3 8D1 =PP3V42_G3H_TPAD 1/16W MF-LF WS_LEFT_SHIFT_KBD 47B5 47B3 7A5 402 47B5 47B3 7A5 WS_LEFT_OPTION_KBD 47B5 47B3 7A5 WS_CONTROL_KBD 47C6 7B5

47A8 47B6

32

=PP3V3_S3_TPAD

IN

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

P2_3 2 P2_1 3 P4_7 4 P4_5 5 P4_3 6 P4_1 7 P3_7 8 P3_5 9 P3_3 10 P3_1 11 P5_7 12 P5_5 13 P5_3 14 P5_1

15

C

1

WS_CONTROL_KEY Z2_KEY_ACT_L Z2_BOOT_CFG1 TP_P4_5 Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK

NC

0.72E-3 W

CRITICAL

P1_7 P1_5 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6

47B4

APN 518S0637

36E-3 W

PSOC PROGRAMMING CONNECTOR

P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4

56

47B4

53

47B4

55

48C3 7B5

J5713

17

47A5

PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY

16

48C1 7B5

CRITICAL

TMP102

47C5 47B5 47A6 8C3

PSOC USB CONTROLLER

31 F-RT-SM

FF14-30A-R11B-B-3H

SMC_MANUAL_RESET LOGIC 47C5 47C2 47B5 8D1

=PP3V42_G3H_TPAD 1

C5758 0.1UF 10% 16V

2 X7R-CERM 402

0.1UF

=PP3V42_G3H_TPAD

47C5 47C2 47B5 47B3 8D1

DIFFERENTIAL_PAIR=USB2_TPAD

e r

R5701 USB_TPAD_P

74B3 20D3

74B3

24

1

47D2 47C5 47B5 47A6 8C3

2

USB_TPAD_R_P

PP3V3_S3_PSOC

5%

47A8 47D7

47C2 47B3 7A5

1/16W MF-LF 402

B

TO MLB CONNECTOR

R5702 USB_TPAD_N

74B3 20D3

74B3

24

1

2

USB_TPAD_R_N

5% 1/16W MF-LF 402

U5701 CHIP DECOUPLING PLACE C5701, C5702 & C5703 CLOSE TO U5701 VDD PIN 22

PLACE C5704, C5705 & C5706 CLOSE TO U5701 VDD PIN 49

P R5704

47B6 47D7

PP3V3_S3_PSOC

1

2

C5701

1


1

C5702

1

C5703

1

C5704

1

C5705

4.7UF

100PF

0.1UF

100PF

0.1UF

20% 6.3V X5R 603

5% 50V CERM 402

10% 16V X7R-CERM 402

5% 50V CERM 402

10% 16V X7R-CERM 402

2

2

=PP3V3_S3_TPAD

2

A

2

1

C5706

1.5

5% 1/16W MF-LF 402

2

2

47D2 47C5 47B5 47A6 8C3

47C2 47B3 7A5


A

1

1

20% 10V CERM 402

WS_LEFT_OPTION_KEY

4

U5726 Y

WS_LEFT_OPTION_KBD

47C5 47C2 47B5 47B3 8D1

DIFFERENTIAL_PAIR=USB2_TPAD

CRITICAL

5

2

APN 311S0406 5 47C2 47B5 7A5

47D8

B

47C2 47B5 7A5 47C2 47B5 7A5

WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

1 A 3 B 6

3

CRITICAL

5

=PP3V3_S3_TPAD

2

WS_CONTROL_KBD

1


A

U5727 Y

1

0.1UF

2

5%

20% 10V CERM 402

WS_CONTROL_KEY

R5769 33K

1

4

SN74LVC1G10 SC70

4

40C7

U5703 Y

SMC_TPAD_RST_L

C

B

2

C5727

=PP3V42_G3H_TPAD

CRITICAL

2

1/16W MF-LF 402

1

R5770

1

33K 1/16W MF-LF 2 402

R5771 33K

5%

2

5% 1/16W MF-LF 402

47C8

B

3

TPAD BUTTONS DISABLE

=PP3V3_S3_TPAD

47D8

BUTTON_DISABLE

8C3 47B5 47C5 47D2

PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

4.7UF

Q5701

20% 6.3V

2 X5R

SSM3K15FV

603

SOD-VESM-HF

WELLSPRING 1

D 3

SYNC_MASTER=YUAN.MA

1 SMC_LID 40C2 39B5 38B4

IN

G

S 2



THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 57

1

109

A

8

6

7

2

3

4

5

1

BOOSTER +18.5VDC FOR SENSORS BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED

APN 152S0504

D

PP5V_S3_TPAD_F

48C7 48B6

D

CRITICAL

L5801

D5802

3.3UH-870MA

0

5% 1/16W MF-LF 402

R5805

2

0

1

MIN_NECK_WIDTH=0.20MM

APN 371S0313

PP18V5_S3

IPD FLEX CONNECTOR

7C3 7C5 48C1

402

1 1

C5818

PP5V_S3_BOOSTER

39PF

APN 353S1401

R5812 1M

APN 516S0689

1% 1/16W MF-LF 2 402

5% 50V CERM 402

2

2

2 5% 1/16W MF-LF

2

5% 1/10W MF-LF 603

0 1

B0520WSXG

SWITCH_NODE=TRUE


PP18V5_S3_SW


MIN_LINE_WIDTH=0.50MM

1

R5800

BOOST_SW VLF3010AT-SM-HF

0.50MM 0.20MM

y r

R5806

SOD-323

INPUT_SW

CRITICAL

J5800

55560-0227

VIN

NO STUFF

1

CRITICAL

8C3

L

VOLTAGE=3V3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

0.01H-0.3A-80V SM-HF

2

QFN

3

DO

5

CTRL

Z2_BOOST_EN

7C5 48C3

SYM_VER-1

48C7 48C4 48B4 7C5

10% 25V X5R 603-1

CRITICAL

48B6 48D6

THRML 2

3

TPAD_GND_F

PAD

7C5 48B4 48C3 48C4

1

VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM


2

1

C5816

C5817

0.1UF

2.2UF

10% 16V X7R-CERM 402

10% 16V X5R 603

2

9

2

20% 10V CERM 402

1

8

SW 6 GND

PP5V_S3_TPAD_F

0.1UF

7 PGND

4

C5800

47C8

1

C

0

47C8

47C8

1/16W

R5811

402

1% 1/16W MF-LF 402

2

48C5

MF-LF

2

100K

47D8 47C8 47B6

48B4 7C5 7C3

R5801 1

R5813 71.5K 1%

Z2_CS_L 7C5 Z2_DEBUG3 7C5 Z2_MOSI 7C5 Z2_MISO 7C5 Z2_SCLK 7C5 Z2_BOOST_EN 7B5 Z2_HOST_INTN Z2_BOOT_CFG1 7B5 7B5 Z2_CLKIN

47C8 7C5

47C8

1 1

48C7 48C3 48B4 7C5 TPAD_GND_F

2

5% 1/10W MF-LF 603

3V3 LDO FOR IPD

m il

R5873 PP5V_S3_TPAD_F

1

48D6 48C7

10

PP5V_S3_VR

2

1% 1/16W MF-LF 402

48C3 7C5 7C3

PP3V3_S3_LDO

TPAD_GND_F

a n i 1UF

BOOST_FB

4

FB TPS61045

L5800

=PP5V_S3_TPAD

U5805

1


0.50MM 0.20MM

C5819

PP3V3_S3_LDO

0.50MM 0.20MM

M-ST-SM

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

0.50MM

Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK =I2C_TPAD_SDA =I2C_TPAD_SCL PP18V5_S3

7B5 47C8 7B5 47C8 7B5 47C8 7B5 47D8 7B5 47C8 7B5 47C8 7B5 47C8 42D1 42D1 7C3 7C5 48D3

0.20MM

C

2 X5R

1

603

P

To detect Keyboard backlight, SMC will tristate SMC_SYS_KBDLED: LOW = keyboard backlight present HIGH= keyboard backlight not present

=PP3V3_S0_TPAD

A

8D5

1%

1/6W MF 402-HF

0.2

1

10%

2

16V X7R-CERM 402

2

C5854 4.7UF 20% 6.3V X5R 603

GND

B

TPAD_GND_F

=PP5V_S0_KBDLED

CRITICAL

1

2

C5850

1

1UF

2

10% 10V X5R 402-1

CTRL

U5850

R5852 1

LT3491

4.7K

5% 1/16W MF-LF 402

2

F-RT-SM

SMC_KDBLED_PRESENT_L

1 2

2

NO STUFF

5% 1/16W MF-LF 402

FF18-4A-R11AD-B-3H 48A6

SW

3

LED

5

CRITICAL

10K

on keyboard backlight flex

J5815

VIN

6

R5854 1

J5815 pin 1 is grounded CRITICAL

KBDLED_SW MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM SWITCH_NODE=TRUE

1098AS-SM

470K

5% 1/16W MF-LF 402

APN 518S0691

L5850 10UH-0.58A-0.35OHM

R5853 1

39B8

R5853 ALWAYS PRESENT

1

0.1UF

PP3V3_S3_LDO_R

3

VOUT

C5838

KEYBOARD BACKLIGHT DRIVNG AND DETECTION

SMC_SYS_KBDLED

IN

BOM OPTION: KBDLED_YES TURNED ON FOR BEST MLB CONFIG

1

1

B

CE

R5836

2

10%

16V

MM3243DRRE MLF

4

C5853 2.2UF

8B5

VDD VR5802

e r 1

2

CRITICAL

APN 353S1364

3 4

7A5 KBDLED_ANODE MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

1

WELLSPRING 2

R5855

SYNC_MASTER=YUAN.MA


10 1%

DFN


1/16W MF-LF

2

CAP

2

THRML

PAD

4


KBDLED_CAP MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 1

7

2

GND

KBD BACKLIGHT CONNECTOR

402

C5855


1UF 2


10% 35V X5R 603

SIZE

SMC_KDBLED_PRESENT_L

DRAWING NUMBER

D

48A4

APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 58

1

109

A

8

6

7

2

3

4

5

1

Digital SMS

D

D

y r

Pull-up required if SMS_INT_L not used.

=PP3V3_S3_SMS

49B7 8C3

ENG_DIGSMS =PP3V3_S5_SMC

ENG_DIGSMS

9

2

40D8 40C7 40C1 39D4 8D1

VDD

R5932

1

10K 5%

1/16W MF-LF 2 402 40B4

OUT

42A3

=I2C_SMS_SCL

6 SCK

11 NC

2

12 NC LGA 8 SDI CRITICAL ENG_DIGSMS 1 NC 4 INT RESERVED 10 NC 5 CSB

42A3

=I2C_SMS_SDA

SMS_INT_L 1

2 402

Stuff R5931 AND NoStuff R5932 to use U5930 NoStuff R5931 AND Stuff R5932 if U5930 is not used

C

m il

Analog SMS R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC =PP3V3_S3_SMS

R59211

VDD

10K

U5920

5% 1/16W MF-LF 402 2

B 39C8

IN

SMS_ONOFF_L

AP344ALH LGA

SMS_PWRDN MAKE_BASE=TRUE

SMS_SELFTEST

1 FS VOUTX 12 5 PD CRITICAL VOUTY 10 2 ST VOUTZ 8

R5922 10K

P 2

A

5% 1/16W MF-LF 402

NC

15 RES 4 RES

NC NC NC

3 NC 6 NC 9 NC

C5922

1

2

20% 4V X5R 603

OUT

39A8

SMS_Y_AXIS

OUT

39A8

SMS_Z_AXIS

OUT

39A8

1

GND

C5923 0.01UF

10% 2 16V CERM 402

2

16V X5R 402

placed on board top-side:

+Y

+X

Front of system

+Z (up)

Circle indicates pin 1 location when placed in correct orientation

C

10UF

10% 16V 2 X5R 402

SMS_X_AXIS

NC 11 NC NC 13 NC NC 16 NC

10% 16V CERM-X5R 402

0.1UF 10%

Desired orientation when

C5926

0.1UF

7

1

1

e r 14

49D6 8C3

C5931 0.022UF

C5932

a n i

GND

ENG_DIGSMS

3

5% 1/16W MF-LF

U5930

273141043NC

7 SDO

PROD_DIGSMS

R5931 10K

1

VDDIO

1

1

C5924 0.01UF

10% 2 16V CERM 402

1

Desired orientation when placed on board top-side:

B +Y Front of system

+X +Z (up)

C5925 0.01UF

Circle indicates pin 1 location when placed in correct orientation

10%

2 16V CERM 402

SMS SYNC_MASTER=YUNWU


A


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 59

1

109

8

6

7

2

3

4

5

1

D

D

41C7 41B5 8A3

y r

a n i

=PP3V3_S5_ROM NO STUFF 10K

R6150 41C5 41A8

IN

SPI_CLK_MUX

PLACEMENT_NOTE=PLACE CLOSE TO U6100 41B5

IN

0

1

SPI_MLB_CS_L

3.3K

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 402 2

1

R6101 3.3K

C6100 1

8

R61901 R61001

C

CRITICAL

VCC

0.1UF

5% 1/16W MF-LF 2 402

20% 10V CERM 2 402

U6100 32MBIT

R6152

SOP

2

74A3 41A1

SPI_CLK

5% 1/16W MF-LF 402

6 SCLK

SI/SIO0 5 74A3 MX25L3205DM2I-12G

1 CE*

SPI_WP_L SPI_HOLD_L

41B1

SO/SIO1 2

74A3

SPI_MISO_R NO STUFF

1

R6191 10K

1

0

5% 1/16W MF-LF 402

2

0

5% 1/16W MF-LF 402

2

SPI_MOSI_MUX

IN

41A8 41C5

PLACEMENT_NOTE=PLACE CLOSE TO U6100

SPI_MISO_MUX

OUT

41A8 41B5

PLACEMENT_NOTE=PLACE CLOSE TO U6100

4

5% 1/16W MF-LF 2 402

e r

MCP79 SPI Frequency Select Frequency 31 MHz 42 MHz 25 MHz 1 MHz

1

R6105

m il 7 HOLD*

GND

B

SPI_MOSI

OMIT

3 WP*/ACC

C

P

SPI_MOSI

SPI_CLK

0

0

0

1

1

0

1

1

B

25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191

A

SPI ROM SYNC_MASTER=CHANGZHANG



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 61

1

109

A

8

6

7

2

3

4

5

1

AUDIO CODEC APPLE P/N 353S1538

CRITICAL

L6202

D

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.6V

FERR-220-OHM 1

ALIAS OF PP3V3_SO, MIN_LINE_WIDTH=0.6MM, MIN_NECK_WIDTH=0.2MM

PP4V6_AUDIO_ANALOG

2

D 7C3 51A3 52D6

0402

y r

CRITICAL

L6201

1

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

2 0402

CRITICAL

10%

5% 1/16W MF-LF 2 402

74A3 21D2

IN

0.01UF

10% 2 25V X7R 402

10% 2 25V X7R 402

HDA_BIT_CLK HDA_SYNC HDA_SDOUT

6 10 5 8

R6204 74A3 21D7

OUT

HDA_SDIN0

2

OUT

CODEC_SDATA_IN

1

AUD_GPIO_0

2 3

C

55C4 55B4

OUT OUT

NO_TEST

NC_AUD_BI_PORT_C_L

PORT C RT=SUB. SPKR SIGNAL SOURCE OUT

1

20% 6.3V TANT CASE-AL1

2

SYNC SDATA_OUT

C6206

1

0.01UF

10% 2 25V X7R 402

SPDIFI/EAPD/MIDI-I/DMIC-R

U6200

23 24

AUD_BI_PORT_C_R AUD_BI_PORT_D_L AUD_BI_PORT_D_R

35 36

PORT-C-L PORT-C-R

NO_TEST18 NO_TEST19 NO_TEST20

10% 2 25V X7R 402

0.01UF GND_AUDIO_CODEC

51A7 51B7 52B6 52C3 52C6 53A8 53B8 53C8 54B3 55A2 55A4 55A8 55B4 55B5 55B8 55C4

a n i 1

22

2

54D3

5% 1/16W MF-LF 402

SENSE_A SENSE_B

13 34

PORT-A-L PORT-A-R

39 41

PORT-F-L

16 17 30 33 NO_TEST 14 15 31 NO_TEST 28 21 22

PORT-F-R

PORT-D-L

PORT-F-VREFO PORT-A-VREFO/DCVOL

PORT-D-R

PORT-E-L

PORT D=HP SIGNAL SOURCE

NC_BAL_IN_L NC_BAL_IN_COM NC_BAL_IN_R

1

2

55C8

AUD_SPDIF_OUT

AUD_SPDIF_I 55A8 AUD_SENSE_A 55C8 AUD_SENSE_B 54B3

OUT

IN IN IN

PORT A = LINE INPUT

REV B3

GPIO0/DMIC-CLK GPIO1/DMIC-L

1

20% 6.3V TANT CASE-AL1

100UF

AUD_SPDIF_O

48 47

CRITICAL

SDATA_IN

C6207

C6205

R6206

SPDIFO

QFN

AUD_GPIO_1

53B8

BCLK

ALC885Q-VB3-GR

5% 1/16W MF-LF 402

HP AMP. SHDN CONTROL 55D3

22

CRITICAL

C6204 100UF

1 9

402

C6203

DVDD

IN

1

0.01UF

6.3V CERM 2

100K

C6201

25 38

R6270

IN

1

1UF

AVDD2

C6200 1

74A3 21C2

AVDD_ADC_DAC

CRITICAL 1

74B3 21D2


CODEC_DVDD

AVDD1

55B5 54D8 52D6 51A7

FERR-220-OHM

DVDD_IO

VOLTAGE=3.3V 8C5 =PP3V3_S0_AUDIO

CD-L

PORT-E-R PORT-E-VREFO

CD-GND CD-R

PORT-B-VREFO PORT-B-L PORT-B-R

AUD_BI_PORT_A_L 55A1 AUD_BI_PORT_A_R 55B1

AUD_BI_PORT_F_L 55A4 AUD_BI_PORT_F_R 55B4 AUD_VREF_PORT_F 55A4

NC_AUD_VREF_PORT_A

52C6

AUD_BI_PORT_E_L

NC_AUD_VREF_PORT_E

IN IN IN

PORT F= MIC INPUT

IN

OUT

PORT F VREF=MIC BIAS

IN

PORT E = MIKEY MIC INPUT

C

SPKR. AMP. SHDN CONTROL

AUD_VREF_PORT_B AUD_BI_PORT_B_L 53C8 AUD_BI_PORT_B_R

53C8 53B8 53A8

OUT

53A8

OUT OUT

PORT B=L AND R SPKR AMP. SIGNAL SOURCE

29 NO_TEST 32 NO_TEST

NC_AUD_VREF_PORT_C NC_AUD_VREF_PORT_D

PORT-G-R


NC_AUD_BI_PORT_G_L NC_AUD_BI_PORT_G_R

PORT-H-L PORT-H-R


NC_AUD_BI_PORT_H_L NC_AUD_BI_PORT_H_R

PORT-C-VREFO

BEEP

12

BEEP

11

RESET*

m il PORT-B-VREFO2 PORT-G-L

CRITICAL

100K

C6208 0.1UF

5% 1/16W MF-LF 2 402

49

10% 16V 2 X5R 402

VREF

NO STUFF

e r 1

R6201 0

B

55A2 54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51A7 55C4 55B8 55B5 55B4 55A8 55A4

5% 1/16W MF-LF 2 402

GND_AUDIO_CODEC MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

P

CRITICAL

L6200

FERR-220-OHM

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

VOLTAGE=5V

55D4 8C3

55B5 54D8 52D6 51D8

=PP5V_S3_AUDIO

8C5 =PP3V3_S0_AUDIO

A 55A2 54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7 55C4 55B8 55B5 55B4 55A8 55A4

1

2

AVSS2

1

AVSS1

R6203

DVSS

1

JDREF NC

AUD_CODEC_VREF 27 40 AUD_CODEC_JDREF 37 NC_VRP 1

CRITICAL

3.3UF 10% 16V TANT SMA-HF

0.1UF

10% 2 16V X5R 402

5% 1/16W MF-LF 2 402

C6212

0.001UF

1

10% 50V 2 CERM 402

2

B

AUDIO 4.6V REGULATOR APPLE P/N 353S1897

MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM PP5V_S3_AUDIO_F

CRITICAL

U6201 MAX8902A PP4V6_ENABLE

5% 1/16W MF-LF 402

C6220

1

C6210

2

1

100K

1% 1/16W MF-LF 2 402

0402

1K

R6209

20.0K

R6202 1

1

R6205

NO_TEST

26 42

HDA_RST_L

THRM_PAD

IN

4 7

74A3 21D2

TDFN

3

EN

1

IN

MAX8902_BP 7

1

R6210

CRITICAL C6223 1 C6221 0.01UF

10K

5% 1/16W MF-LF 2 402

10% 25V X7R 402

10UF

2

20% 6.3V X5R 603

1

C6224 0.01UF

10% 50V 2 X7R 603-1

SELA SELB

4 5

OUT OUTS

8 6

PP4V6_AUDIO_ANALOG 7C3 51D3 52D6

BP GND 2

CRITICAL THRML PAD 9

1

C6222 10UF

2

20% 6.3V X5R 603

1

C6225 0.01UF

AUDIO: CODEC

10% 2 25V X7R 402

SYNC_MASTER=AUDIO



GND_AUDIO_CODEC


XW6200 SM 1


2

PLACE XW6200 AND XW6201 NEAR U6201

STAR GND PT. FOR AUDIO SYSTEM


XW6201 SM 53C4 53B3 53A4

GND_SPKR_AMP

1

SIZE

DRAWING NUMBER

D

2

APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 62

1

109

A

8

6

7

2

3

4

5

1

MIKEY RECEIVER CKT

D

MIKEY

D

L6301

FERR-1000-OHM

y r

PP4V6_AUDIO_ANALOG 51D3 51A3 7C3

0402

NO STUFF

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM

L6300

FERR-1000-OHM =PP3V3_S0_AUDIO 0402

10% 16V X5R 603

=I2C_MIKEY_SCL

MIKEY CRITICAL AVDD 3

0

5% 1/16W MF-LF 402

U6300 CD3275 DRC

MIKEY

R6306 BI

0

=I2C_MIKEY_SDA

5% 1/16W MF-LF 402

MIKEY

AUD_I2C_INT_L

C

21C3 21A4

R6307

6

SCL

MICBIAS

1

HS_SDA

5

SDA

DETECT

2

HS_INT_L

7

INT*

BYPASS

10

HS_RST

8

ENABLE GND

MIKEY

0

R6301

OUT

47K PULL-UP ON MCP PAGE (R2142)

4

42B6

HS_SCL

2.2UF

IN

AUD_IPHS_SWITCH_EN

0.01UF 10% 25V X7R 402

GND_AUDIO_CODEC

MIKEY

R6302 10K 1% 1/16W MF-LF 402

0

5% 1/16W MF-LF 402

20% 6.3V TANT 402

C6302

THM

5% 1/16W MF-LF 402

MIKEY

C6301

HS_RX_BP

R6308 19D7

MIKEY CRITICAL

HS_SW_DET

MIKEY

100K

5% 1/16W MF-LF 402

HS_MIC_BIAS

11

IN

a n i

2.2UF

MIKEY

R6305 42B6

CRITICAL MIKEY

C6300

PLACE R6301, R6305, R6306, R6307, AND R6308 OUTSIDE AUDIO SECTION TO CONSERVE AUDIO AREA

9

55B5 54D8 51D8 51A7 8C5

AVDD_S0_HS

GND_AUDIO_CODEC 55A2 54B3 53C8 53B8 53A8 52C3 52B6 51D3 51B7 51A7 55C4 55B8 55B5 55B4 55A8 55A4

MIKEY

C6303 51C3

m il

0.1UF

AUD_BI_PORT_E_L OUT

10% 16V X7R-CERM 402

OMIT

R6304 100K

XW6300 SM 55A2 54B3 53C8 53B8 53A8 52C6 52C3 51D3 51B7 51A7 55C4 55B8 55B5 55B4 55A8 55A4

GND_AUDIO_CODEC

5% 1/16W MF-LF 402

OMIT

C6304

0.001UF 10% 50V CERM 402

NOSTUFF

R6300

C

51A7 51B7 51D3 52B6 52C6 53A8 53B8 53C8 54B3 55A2 55A4 55A8 55B4 55B5 55B8 55C4

MIKEY

R6303 2.2K 5% 1/16W MF-LF 402

HS_MIC_HI

HS_MIC_LO

IN

54D3

IN

54D3

0

PART#

B

QTY

e r

DESCRIPTION

A

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

116S0114

1

100K 5% 0402 RESISTOR

R6304

116S0004

1

0 OHMS 5% 0402 RESISTOR

R6304

132S0045

1

100PF 50V 10% 0402 CAPACITOR

C6304

116S0004

1

0 OHMS 5% 0402 RESISTOR

C6304

P

5% 1/16W MF-LF 402

CRITICAL

BOM OPTION

?

MIKEY

?

NOMIKEY

TABLE_5_ITEM

B

TABLE_5_ITEM

TABLE_5_ITEM

?

MIKEY

?

NOMIKEY

TABLE_5_ITEM

AUDI0: MIKEY SYNC_MASTER=AUDIO



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 63

1

109

A

8

6

7

SATELLITE

D

& SUB TWEETER AMPLIFIER

2

3

4

5

APN:353S1595

SATELLITE

169 HZ < FC < 282 HZ

SUB GAIN

80 HZ < FC < 132 HZ 12DB

D

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 53C8 53B8 8C3

y r

VOLTAGE=5V =PP5V_S3_AUDIO_AMP

CRITICAL

C6607 1

C6602 1

1uF

10% 6.3V CERM 2 402

CRITICAL

L6610

51C3

IN

1

AUD_SPKRAMP_INR_L

2

1

R6610

AUD_VREF_PORT_B

0

1

IN

C

55C4 55B8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 55B5 55B4 55A8 55A4 55A2 54B3 53B8

2 IN+ 3 IN-

SPKRAMP_R_SHDN

CRITICAL

5 SHDN*

2

C6601

a n i

100UF

10% 6.3V CERM 2 402

20% 2 6.3V TANT CASE-AL1

TDFN1

MAX9705_R_N

OUT+ OUT-

8

SYNC

6

9

NO STUFF 1

R6601

THRML GND PGND PAD

CRITICAL

C6611 1

5% 1/16W MF-LF 402

1UF

10 PVDD

U6610

2

10% 16V X7R 402

1

MAX9705

0.047UF AUD_SPKRAMP_INR

0402

53B8 53A8 51C3

1 VDD

C6610

FERR-1000-OHM AUD_BI_PORT_B_R

7

4

0.047UF

100

5% 1/16W MF-LF

11

2 402

10% 16V X7R 2 402

GND_AUDIO_CODEC

0

1

=PP5V_S3_AUDIO_AMP

GND_SPKR_AMP

2

L6620

AUD_BI_PORT_C_R 51C7

1

IN

2

AUD_SPKRAMP_INSUB_L

0402

1

IN

0

0.1UF 10% 16V X5R 402

R6609

AUD_VREF_PORT_B 53C8 53A8 51C3

m il 10% 6.3V CERM 2 402

C6620

FERR-1000-OHM

AUD_SPKRAMP_INSUB SPKRAMP_SUB_SHDN

2

0.1UF

e r

GND_AUDIO_CODEC

B ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

=PP5V_S3_AUDIO_AMP

P CRITICAL

L6630

FERR-1000-OHM AUD_BI_PORT_B_L 51C3

IN

1

2 0402

53C8 53B8 51C3

IN

C6630

AUD_SPKRAMP_INL_L

10% 16V X7R 402

AUD_VREF_PORT_B

100K 5% 1/16W MF-LF 402

GND_AUDIO_CODEC

A

2 IN+ 3 IN-

OUTCRITICAL SYNC 5 SHDN*

6

0

2

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT 7C7

SPKRAMP_SYNC2

54C2

53A4

GND_SPKR_AMP

51A6 53A4 53C4

NO STUFF

R6606 0

1

B

2

5% 1/16W MF-LF 402

CRITICAL

C6606 1

1 VDD

1uF

10% 6.3V CERM 2 402

1

1UF

100UF

10% CERM 2 402

10 PVDD


6.3V

U6630

C6605

1

R6603 0

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT 7C7

5% 1/16W MF-LF 2 402

MAX9705

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT

TDFN1

2 IN+ 3 IN-

MAX9705_L_N

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT 7C7 54C2

5% 1/16W MF-LF 2 402

GND PGND PAD 4 7 11

C6609 1

R6608

0


8 9

OUT+

R6604

100UF

10% 6.3V CERM 2 402

10 PVDD

U6620

AUD_SPKRAMP_INL

1

R6611

55C4 55B8 53B8 52C6 52C3 52B6 51D3 51B7 51A7 55B5 55B4 55A8 55A4 55A2 54B3 53C8

0.047UF

C

1

C6603

THRML

CRITICAL

C6621 10% 16V X5R 402

53D8 53C8 8C3

1

1UF

MAX9705 TDFN1

MAX9705_SUB_N

5% 1/16W MF-LF 402

53C8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 55C4 55B8 55B5 55B4 55A8 55A4 55A2 54B3

1 VDD

1

1uF

CRITICAL

54C2

51A6 53A4 53B3

CRITICAL

C6604 1

C6608

54C2

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT 7C7


5% 1/16W MF-LF 402

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT 7C7

SPKRAMP_SYNC1 53A3

NO STUFF

R6605

53D8 53B8 8C3

1

OUT-

8 9

CRITICAL SYNC

6

OUT+

5 SHDN*

SPKRAMP_L_SHDN

THRML

CRITICAL

C6631

7C7 54C2

SPKRAMP_SYNC1 53C4

NO STUFF

GND PGND PAD 4 7 11

54C2

1

R6602 100

5% 1/16W MF-LF

2 402

0.047UF 10% 16V X7R 402

SPKRAMP_SYNC2 53B3

AUDI0: SPEAKER AMP GND_SPKR_AMP 51A6

53B3 53C4

SYNC_MASTER=AUDIO

NO STUFF

0

1



R6607 2


5% 1/16W MF-LF 402


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 66

1

109

A

8

6

7

2

3

4

5

1

AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX

MIC CONNECTOR

AUD_SPDIF_OUT IN

R6790 55B5 52D6 51D8 51A7 8C5

=PP3V3_S0_AUDIO

0

1

D 54B8

78171-0003 M-RT-SM 4

HS_MIC_HI OUT

L6710

54B1 7D7 55A6 7D7

OUT

AUD_CONNJ1_SLEEVE

CRITICAL

AUD_CONNJ1_SLEEVE_F

0

0

AUD_CONNJ1_TIPDET

AUDIO-JACK-TRANS-M97 5 2 1


4

8 9

POF 1

10 11

1UF

10% 2 6.3V CERM 402

12

1

AUD_CONNJ1_SLEEVEDET_F

DZ6704 6.8V-100PF

R6701

402

4.7

1

6.8V-100PF CRITICAL

2

2

DZ6702 6.8V-100PF

CRITICAL

5% 1/16W MF-LF 402

CRITICAL

DZ6705

6.8V-100PF

6.8V-100PF

m il

402

402

1

1

1

AUD_J1_TIPDET_R

2

2

1

DZ6703

402

APN:514-0607

AUD_J1_SLEEVEDET_R

2

5% 1/16W MF-LF 402

CRITICAL

2

10K

1

C6705 100PF

1

5% 2 50V CERM 402

=GND_CHASSIS_AUDIO_JACK


R6760 CHASSIS GND BAND AID 0 5% 1/16W MF-LF 402

R6749 AUD_J2_OPT_OUT

B

54D8

5% 1/16W MF-LF 402

PP3V3_S0_AUDIO_SPDIF

R6752 0

AUD_CONNJ2_SLEEVE CRITICAL

J6750 F-RT-TH3 5 2

R6753

AUD_CONNJ2_TIPDET

0

1

AUD_CONNJ2_TIP

3 4

A - VDD B - GND C - VOUT

6 7 8

OPERATING VOLTAGE 3.3

POF 9

SHELL SHIELD PINS

P

AUD_CONNJ2_RING

AUDIO

10 11 12

R6754

1

C6750 1UF

A

APN:514-0608

10% 2 6.3V CERM 402

5% 50V CERM 402

CRITICAL

J6703 78171-0004

100PF 5% 50V CERM 402

1 2

C

3 4

6

APN:518S0521

100PF 5% 50V CERM 402

53C3 7C7

IN

SPKRAMP_R_N_OUT

C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES

55C1

2

GND_AUDIO_CODEC

MIC EMI FILTER

51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 55A2 55A4 55A8 55B4 55B5 55B8 55C4

L6770

L6771

FERR-1000-OHM MIC_LO 55A6

OUT

51C2

OUT

1

2

FERR-1000-OHM

MIC_LO_CONN_F

1

0402

MIC_LO_CONN

2

7D7 54D2

0402

B L6772

L6773

FERR-1000-OHM MIC_HI 55A6

OUT

1

FERR-1000-OHM MIC_HI_CONN_F

2

1

MIC_HI_CONN

2

0402

7D7 54D2

0402 CRITICAL 2

DZ6770 6.8V-100PF 402

AUD_PORTA_R

BI

CRITICAL

55A3

2

1

DZ6771

1

1

2

AUD_PORTA_L

BI

55B3

0402

55A4 9C8

R6750

402

CRITICAL

2

CRITICAL

DZ6755 402

1 1

1

AUDIO: JACK R6751

6.8V-100PF 1

402

=GND_CHASSIS_AUDIO_MIC

2

5% 1/16W MF-LF 402

2

CRITICAL

10K

1

4.7

2

SYNC_MASTER=AUDIO

AUD_J2_TIPDET_R OUT

55A8

C6756 100PF



5% 1/16W MF-LF 402


5% 2 50V CERM 402


=GND_CHASSIS_AUDIO_JACK


DRAWING NUMBER

D

AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX

APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

8

M-RT-SM 5

C6761

402

6.8V-100PF

402

100PF

C6763

FERR-1000-OHM

DZ6754

6.8V-100PF

C6760

6.8V-100PF

DZ6753 1

4

5% 50V CERM 402

L6756

1

54B8 9C8

AUD_LO_GND

2

AUD_SPDIF_I

2

AUD_CONNJ2_SLEEVEDET_F

2

2

100PF

0402

6.8V-100PF CRITICAL

1

C6762

L6754

1

R6756

DZ6752

IN

SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT

SPKRAMP_SUB_N_OUT SPKRAMP_R_P_OUT

FERR-1000-OHM

AUD_CONNJ2_TIP_F

2

53C3 7C7

IN

2

5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

IN

IN

53A2 7C7

SPKRAMP_SUB_P_OUT

IN

53B2 7C7

53B2 7C7

55C8

OUT

XW6701 SM 1

53B2 7C7

0402-LF

R6755

0

M-RT-SM 3

L6751

1

5% 1/16W MF-LF 402

0

J6702 78171-0002

FERR-120-OHM-1.5A

AUD_CONNJ2_RING_F

0

AUD_CONNJ2_SLEEVEDET

55B6 55B8

OUT

AUD_CONNJ2_TIPDET_F

5% 1/16W MF-LF 402

5

CRITICAL

CRITICAL

AUD_CONNJ2_SLEEVE_F

5% 1/16W MF-LF 402

AUDIO-RCVR-M97

1

AUD_J2_COM

e r

22

3

XW6700 SM

AUD_J1_COM

NOSTUFF

55C1 55D1

BI

R6700

CRITICAL

402

AUD_LO_AMP_OUTL

2 0402

DZ6706

13

BI

FERR-1000-OHM

AUD_CONNJ1_TIP_F

5% 1/16W MF-LF 402

C6700

AUD_LO_AMP_OUTR

L6706


R6707 0

a n i

2

5% 1/16W MF-LF 402

OPERATING VOLTAGE 3.3

54A8 9C8

1 0402

0

AUD_CONNJ1_SLEEVEDET

7

FERR-1000-OHM

AUD_CONNJ1_RING_F

R6706

AUD_CONNJ1_RING

AUDIO

L6704


5% 1/16W MF-LF 402

AUD_CONNJ1_TIP

3

SHIELD PINS

AUD_CONNJ1_TIPDET_F

0


2

APN:518S0519

0402-LF

R6705

6

SHELL

2

5% 1/16W MF-LF 402

J6700

C

1

D

1

SPEAKER CONNECTOR

L6701

FERR-120-OHM-1.5A

5% 1/16W MF-LF 402

R6704

52B3

0402


R6703


A - VIN B - VCC C - GND

y r

HS_MIC_LO AUD_CONNJ1_MIC

MIC_LO_CONN MIC_HI_CONN MIC_SHLD_CONN

54B1 7D7

FERR-1000-OHM

PP3V3_S0_AUDIO_SPDIF

F-RT-TH3

52C3

0402

5% 1/16W MF-LF 402

CRITICAL

J6701

FERR-1000-OHM AUD_CONNJ1_MIC_F

0

5% 1/16W MF-LF 402

CRITICAL

APN:518S0520

L6709

R6702

2

51C3

A

OF 67

1

109

A

6

7

2

3

4

5

HP/LO AMP APN:353S1637 PORT D HP/LO

L6880

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 51A7 8C3 =PP5V_S3_AUDIO

CODEC OUTPUT SIGNAL PATHS FUNCTION HP OUT SAT SPKRS SUB SPKR SPDIF OUT

VOLUME 0X0C (12) 0X0D (13) 0X0F (15) N/A

CONVERTER 0X02 (2) 0X03 (3) 0X05 (5) 0X06 (6)

PIN COMPLEX 0X14 (20,PORTD) 0X18 (24,PORTB) 0X1A (26,PORTC) 0X1E (30,SPDIF OUT)

MUTE CONTROL GPIO 0 VREF_B(100%) VREF_B(100%) N/A

FERR-120-OHM-1.5A 1

2 0402-LF

DET ASSIGNMENT 0X14 (20,PORTD) N/A N/A 0X16 (22, PORTG)

1

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM AUD_PP5V_F

C6880 0.1UF

10% 2 16V X7R-CERM 402

D

55C2 55B2

1

1

C6881 10UF

20% 6.3V 2 X5R 603

MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM 12

8

VDD CRITICAL

6 INL 8 INR

AUD_LO_AMP_INL_M AUD_LO_AMP_INR_M

U6801

MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM OUTL 11 OUTR 10

y r MAX9724A

MAX9724_C1P

CONVERTER 0X08 (8) 0X07 (7) 0X0A (10)

PIN COMPLEX 0X15 (21,PORTA) 0X19 (25,PORTF) 0X1F (31,SPDIF IN)

VREF N/A VREF_F (80%) N/A

10K

DET ASSIGNMENT 0X15 (21,PORTA) N/A N/A

5% 1/16W MF-LF 402

4 PVSS

MUTE CONTROL 0X08 (8) 0X07 (7) N/A

9 SVSS

VOLUME 0X08 (8) 0X07 (7) N/A

2 PGND

MIXER 0X23 (35) 0X24 (36) N/A

13 THRM PAD

FUNCTION LINE IN MIC IN SPDIF IN

R6885

7 SGND

CODEC INPUT SIGNAL PATHS

CRITICAL

GND_AUDIO_CODEC

a n i 1

2

PLACE CLOSE TO U6801

55A8 51C2

OUT AUD_SENSE_A

55B8 55B4 55A8

PP3V3_S0_AUDIO_F

AUD_OUTJACK_INSERT_L

C

R6805

5.11K

10K

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1

R6801

5% 1/16W MF-LF 2 402

SSM6N15FEAPE

IN

Q6801 2

47K

AUD_J1_TIPDET_R

1

2

G

S 1

NC

AUD_PORTG_DET_L

Q6801

D 3

SSM6N15FEAPE

SSM6N15FEAPE

SOT563

SOT563

1

5

C6801

G

S 4

2

C6886

m il

S 1

16V

10% X5R

402

GND_AUDIO_CODEC

R6803 1

PP3V3_S0_AUDIO_F

5% 1/16W MF-LF 402

1

R6861 270K

5% 1/16W MF-LF 2 402 55B6 54C3

100K 2

AUD_J1_SLEEVEDET_INV

PLACE L6800/C6800 CLOSE TO Q6800 L6800

Q6800

D 3

55B8 54C3

FERR-1000-OHM

AUD_J1_SLEEVEDET_R

SSM6N15FEAPE

54D8 52D6 51D8 51A7 8C5

SOT563

1

2

PP3V3_S0_AUDIO_F

1

5

G

e r

S 4

1

B

C6802 0.01UF 10% 16V

2 CERM 402 55C4 55B8 55B5 55B4 55A8 52C6 52C3 52B6 51D3 51B7 51A7 55A4 55A2 54B3 53C8 53B8 53A8

GND_AUDIO_CODEC

55C8 51C2

AUD_SENSE_A

P

R6813 55C8 55B8 55B4

39.2K

PP3V3_S0_AUDIO_F

1% 1/16W MF-LF 402

1

R6811

AUD_INJACK_INSERT_L

270K

2

5% 1/16W MF-LF 402

Q6802 SSM3K15FV SOD-VESM-HF

R6812 54A3

AUD_J2_TIPDET_R

IN

1

47K 5% 1/16W MF-LF 402

A

2

1

C6811 0.1UF 10% X5R

16V

402

1

G

IN

MIC_HI

CRITICAL

1

51C7

IN

AUD_BI_PORT_D_L

2.2UF AUD_LO_AMP_INL_C 1

2

R6883 13.7K2

1

AUD_LO_AMP_INL_M 55D3

IN

AUD_BI_PORT_D_R

1

2

13.7K2

AUD_LO_AMP_INR_C 1

20% 6.3V TANT 402

AUD_LO_AMP_INR_M 55D3

1% 1/16W MF-LF 402

1

GND_AUDIO_CODEC

5% 1/16W MF-LF 2 402

54B3

IN

PORT A LI CRITICAL

C6832 2.2UF 54A3

IN

2

R6836

51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3 55A2 55A4 55A8 55B5 55B8 55C4

1

50V

CERM 402

GND_AUDIO_CODEC

1% 1/16W MF-LF 402

2

54A3

1

IN

0

IN

CRITICAL 2

C6833 2.2UF

AUD_PORTA_R

AUD_BI_PORT_A_R OUT

2

AUDIO: JACK TRANSLATORS

5% 1/16W MF-LF 402

S 2

SYNC_MASTER=AUDIO

0 2

GND_AUDIO_CODEC



R6854 1

51C3

20% 6.3V TANT 402

51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3 55A2 55A8 55B4 55B5 55B8 55C4

R6853 MIC_SHLD_CONN

51A7 51B7 51D3 52B6 52C3 52C6 53A8 53B8 53C8 54B3 55A4 55A8 55B4 55B5 55B8 55C4

1

27.4K

51C3

NO STUFF

D 3

51C3

20% 6.3V TANT 402

2

51C3

NO STUFF

GND_AUDIO_CODEC

2

AUD_BI_PORT_A_L OUT 1

27.4K

PLACE C6852 NEAR U6200

5% SM

MIC_LO

AUD_BI_PORT_F_R

100PF

XW6800

AUD_PORTA_L

R6837 1

B

51C3

CRITICAL

C6852

2

5% 25V CERM 402

1% 1/16W MF-LF 402

CRITICAL

R6852 100K

10%

CERM 402

1

10% 16V X5R 402 1

1

680PF 50V

220PF

0.1uF

CRITICAL

2

CRITICAL

C6850 AUD_BI_PORT_F_L MAKE_BASE=TRUE

21K

C6891

16V

2

54C3 55D1

1% 1/16W MF-LF 402

603

1

AUD_LO_AMP_OUTR

R6888

55A8 55B8 55C8

6.3V

MIC_IN

54C3 55D1

R6886

2.2UF

51C7

20%

2

AUD_LO_AMP_OUTL

CRITICAL

C6889

AUD_VREF_PORT_F

5% 402

2

1% 1/16W MF-LF 402

X5R 402

2

C

1% 1/16W MF-LF 402

C6853

330

2

5% 1/16W MF-LF 402

2

21K

1

5% 402

R6851

0

1

R6884

10UF

1

C6851

1

1/16W MF-LF

R6882

5% 25V CERM 402

20% 6.3V TANT 402

2 X5R

1/16W MF-LF

54D2 7D7

AUD_J2_DET_RC

2 55C4 55B8 55B5 55B4 52C6 52C3 52B6 51D3 51B7 51A7 55A4 55A2 54B3 53C8 53B8 53A8

NC

54B3

VREF_PORT_F_R

2

1% 402

NO STUFF

10% 2 10V X5R 402-1

1

MIC INPUT CIRCUITRY 2.2K

1

LINE-IN (PORT A) DETECT

GND_AUDIO_CODEC

R6855

1UF

220PF

10%

6.81K

C6885

CRITICAL

0.1UF

R6850

1/16W MF-LF

1% 1/16W MF-LF 2 402

C6888

C6800

2

54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 55C4 55B8 55B4 55A8 55A4 55A2

2.21K

1% 1/16W MF-LF 2 402

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.4MM AUD_LO_GND 54B3

0402

AUD_J1_SLEEVEDET_R

IN

=PP3V3_S0_AUDIO

1

10% 2 10V X5R 402-1

CRITICAL

0.1UF 2

55C8 55B4 55A8

NC

D 6

G

2.21K

10% 2 10V X5R 402-1

MAX9724 GAIN/FILTER COMPONENTS AV_PB = -1 V/V, FC_HPF=5.28HZ, FC_LPF=34.45KHZ

AUD_J1_DET_RC

5% 1/16W MF-LF 402

55C4 55B8 55B5 55B4 55A8 52C6 52C3 52B6 51D3 51B7 51A7 55A4 55A2 54B3 53C8 53B8 53A8

AUD_PORTD_DET_L

SOT563

R6802 54C3

D 6

Q6800

270K

PORT G DETECT(SPDIF DELEGATE)

R6806

=GND_CHASSIS_AUDIO_MIC


9C8 54A3

5% 1/16W MF-LF 402


NO STUFF


R6856 0 1

SIZE

2

DRAWING NUMBER

D

5% 1/16W MF-LF 402

APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

8

D

CRITICAL

C6884 1UF

XW6880 SM

PORT D DETECT

54C3 55B1

MAX9724_SVSS

54B3 53C8 53B8 53A8 52C6 52C3 52B6 51D3 51B7 51A7 55B8 55B5 55B4 55A8 55A4 55A2

OUT AUD_SENSE_B

AUD_LO_AMP_OUTR

R6880 1R6881

C6882 1UF

MAX9724_C1N

1

51C2

1

C1P 1 C1N 3

5 SHDN*

54C3 55C1

1

CRITICAL

TQFN

AUD_GPIO_0 51C7

AUD_LO_AMP_OUTL

A

OF 68

1

109

A

8

6

7

2

3

4

5

1

MagSafe DC Power Jack CRITICAL

J6900

CRITICAL

78048-0573

F6905

M-RT-SM

MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

Vgs(max) = 8V

PP18V5_DCIN_ONEWIRE MIN_LINE_WIDTH=0.25mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

R6917 1

1

270K

0.1UF If ADAPTER_SENSE > Vth then turn off FET

2

100K

R6915 1

ONEWIRE_DCIN_DIV

V+

SOT23-5-HF 4 ONEWIRE_OVERVOLT

V-

5% 1/16W MF-LF 402

Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2

Q6915

R6920

G

S 2

1

2 5% 1/8W MF-LF 805

HN2D01JEAPE

Supply needs to guarantee 3.31V delivered to SMC VRef generator 4

BATT_POS_F MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 mm VOLTAGE=12.6V

NC

2

PPVIN_G3H_P3V42G3H

NC


C6990

P3V42G3H_BOOST

3

1

10% 25V X5R 805

6

VIN

10UF

C6994

BOOST

2

e r LT3470ETS8

NC

B

1

SHDN*

2

NC

4

BAT-M98 F-RT-SM 10

L6950 FERR-50-OHM 7B7


2 3 4

2

6

RCLAMP2402B SC-75

11

2

D6950

8

GND_BATT_CONN MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=0V

1

C6956

1

C6950

2

10% 25V X5R 402

47PF 5% 50V CERM 402

L6951

5 7

FB

8

33UH

NTUD3127CXXG

G

10% 50V CERM 402

CRITICAL

C6995 22pF

2

5% 50V CERM 402

56A3 8D1

SYS_ONEWIRE

1

C6960 0.1UF

10% 16V 2 X5R 402

8D2

R6960 1/16W 402 MF-LF 5% 5

2

39B8 40B2

BI

U6960

74LVC1G17DRL (SMC_BIL_BUTTON_L)

SOT-553 4

2

SMC_BIL_BUTTON_L

1

1

20% 6.3V CERM 805

TO SMC

3

C6961 0.01UF

10% 2 25V X7R 402

200K

1% 1/16W MF-LF 402 2

Vout = 1.25V * (1 + Ra / Rb)

CRITICAL

J6955

BATTERY SIGNAL CONNECTOR

78171-0005 M-RT-SM

6 1 2 3

1

0.1UF

4

2

DC-In & Battery Connectors =PP3V42_G3H_BATT =SMBUS_BATT_SDA =SMBUS_BATT_SCL 7A7 SMC_BIL_BUTTON_DB_L

OUT BI

SYNC_MASTER=JACK

8D1 56B3 42C3 56A6

BI



42C3 56A6


5


7

2

C6954

C6952

1

0.001UF SM-LF

518S0588

10% 50V CERM 402

1

47PF 5% 50V CERM 402

2

C6951

1

0.1UF 2

10% 25V X5R 402

C6953

1


47PF 2

5% 50V CERM 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 2

SIZE

APPLE INC.

DRAWING NUMBER

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

7

39C5

NC

C6999

D

8

B OUT

NC

22UF

R6996 1

C

10K

CRITICAL

P3V42G3H_FB

2

=PP3V42_G3H_BATT

(Switcher limit)

1

39C5 40B2 40D5

SSM6N15FEAPE

348K

1% 1/16W MF-LF 402 2

IN

SOT563

200mA max output

1

SMC_BC_ACOK

2

5% 1/16W MF-LF 402

1

Q6920

Vout = 3.425V

R6995 1

1

C6910

2

CDPH4D19FHF-SM

1K

SMC_BC_ACOK_RC

2

0.001UF

2

4

SYS_ONEWIRE_BILAT

R6910

SOT-963

BIL BUTTON DEBOUNCE CIRCUIT

=PP3V42_G3H_REG

1

P3V42G3H_SW

CRITICAL

Q6910

1

5

SOT563

L6995

2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

3

FERR-50-OHM 7A7

1

CRITICAL

20% 6.3V X5R 402

2

42C3 56A3

CRITICAL

9

BATT_POS_F

42C3 56A3

7

516S0698

57A2 56B8

SM-LF

=SMBUS_BATT_SCL =SMBUS_BATT_SDA SMC_BS_ALRT_L

5

A

1

PPVBAT_G3H_CONN_F

1

1

P

BATTERY POWER CONNECTOR

J6950

SW

BIAS

CRITICAL

GND

D

1

0.22uF

U6990 TSOT23-8

CRITICAL

m il

5

1

3 57A2 56A7

3.425V "G3Hot" Supply

SOT665

PPDCIN_S5_P3V42G3H MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

5% 1/16W MF-LF 402

N-CHN

S

SSM6N15FEAPE

D

1

6

10% 50V CERM 402

Q6920

3

47

=PP18V5_DCIN_CONN

C6917

0.001UF

1% 1/16W MF-LF 402

D6905

R6905 56D1 8C2

2

ONEWIRE_PWR_EN_L

1

2

2

R6912 1 470K

VOLTAGE DIVIDER FROM DCIN ENSURES Q6910 Vgs is met when SYS_ONEWIRE is high or low. Q6920 used as bilateral switch to ensure SYS_ONEWIRE doesn’t drive unpowered U6990 CRITICAL

24.3K

2

5% 1/16W MF-LF 402

a n i

270K

2

C

270K CRITICAL

SSM3K15FV

R6916 1

2

1

y r

Vgs = 7.30V @ 20V DCIN Vgs = 4.74V @ 13V DCIN

SOD-VESM-HF

3

ONEWIRE_ESD

100K 5% 1/16W MF-LF 402

LM397

R6918 1

D 3

G

R6914 1

5% 1/16W MF-LF 402 2

U6915

5

2

ONEWIRE_PWR_EN_L_DIV

270K

CRITICAL

2

5% 1/16W MF-LF 402

2

ONEWIRE_EN

1

S

5% 1/16W MF-LF 402

180K

D

10% 25V X5R 402

R6911 1

6

R6913 1

5% 1/16W MF-LF 402

2

C6915 ADAPTER_SENSE_R

D

SOT-963

1

518S0656

Q6910

4

2 5% 1/16W MF-LF 402

8C2 56B8

NTUD3127CXXG

1-Wire OverVoltage Protection

20% 50V CERM 603

S

2

5

1

C6905 0.01UF

0

ADAPTER_SENSE

3

7B7

G

1

R6928

4

=PP18V5_DCIN_CONN

CRITICAL

1206-1

S

3

2

D

2

5

1

PP18V5_DCIN_FUSE

G

7B7

P-CHN

1

D

Q6910 restricts system load to 10K-70K window until adapter detects system and enables 16.5V output.

6AMP-24V

A

OF 69

1

109

A

8

6

7

2

3

4

5

1

PBUS SUPPLY / BATTERY CHARGER Q7001 HAT1127H LFPAK-SM

CRITICAL

Q7000

S

MIN_LINE_WIDTH=0.6 MM

PPVDCIN_G3H_PRE

2 3

LFPAK-SM

D

PPVDCIN_G3H_PRE2

HAT1127H

CRITICAL

5

=PP18V5_G3H_CHGR


MIN_NECK_WIDTH=0.3 MM


1

R7010

G

5

1

CHGR_SGATE

30.1K 1%

CHGR_DCIN

1/16W MF-LF 402

57C5

4

57.6K

57B5 44B3 57A8

2

R7061 1

VCC

57A8

C7041

VDD

2

R7045 56.2K

1

1% 1/16W MF-LF 402 2

C7044 0.01UF

10% 2 16V CERM 402

CHGR_VCOMP_R

C7045 1

C7043 0.1UF 1

2

10% 16V X5R 402

AMON 9 BMON 15 ACOK 14

57C4 57B8

CHGR_VNEG_R

(CHGR_CSOP)

C7046 1 470PF

10% 50V CERM 2 402

(CHGR_CSON)

=PP3V42_G3H_CHGR

Q7070

1

R7074

SSM6N15FEAPE SOT563

1M

2 G CHGR_VDD_L

D 3

SSM6N15FEAPE SOT563 CHGR_VDD

5 G

R7075

S 4

S 1

5% 1/16W MF-LF 402 2

1 2

0.1UF

0.1UF

10% 25V X5R 402

10% 25V X5R 402 GND_CHGR_SGND 57B6

2

C7020

2

20% 25V POLY-TANT CASE-D2-SM

1

C7021

2

20% 25V 2 POLY-TANT CASE-D2-SM

22UF

22UF

C7022 1

1

1UF

10% 25V X5R 603-1

2

C7023

1

10% 25V X5R 603-1

2

1UF

m il 0.1UF 10% 25V X5R 402

2

C

20% 50V CERM 402

CRITICAL

Q7020

CRITICAL

RJK0305DPB LFPAK-HF

C7025 1

C7027

0.001UF

5

57B8

4

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

1

1 2 3

1

1

4.7UH-9.5A

1 3

2 4

PPVBAT_G3H_CHGR_OUT 1

CRITICAL

IHLP4040DZ-SM

5

1206

0.5% 1W MF 0612


1

4

C7011 1 1UF

C7008

10% 25V

33UF

2

2 X5R

20% 16V POLY-TANT CASED2E-SM

603-1

CRITICAL

2

GND_CHGR_SGND

1

2

57A5

C7028 0.001UF 20% 50V CERM 402

PWM FREQ. = 400 kHz MAX CURRENT = 7A

Q7021

C7026 0.001UF

RJK0305DPB LFPAK-HF

10% 2 50V X7R 402

1 2 3

(??? limited)

R7031 10

77D3 44A8

5% 1/16W MF-LF 402

R7047 10

77D3 44A8

CHGR_CSO_R_N

5% 1/16W MF-LF 402

(CHGR_CSO_R_N)

57B1

B

CHGR_CSO_R_P

BATTERY INRUSH FETS

Q7050 Q7052

CRITICAL

FDS6681Z

CRITICAL

FDS6681Z

SO-8

PPVBAT_G3H_CHGR_OUT 1

C7050 0.01uF

10% 2 16V CERM 402

1

C7051 0.1UF

10% 2 16V X5R 402

TO BATTERY

SO-8

BATT_POS_INRUSH

BATT_POS_F 1

CHGR_BGATE

57C5

C7052 0.1UF

10% 16V 2 X5R 402

56A7 56B8

R7052 1M 5% MF-LF 402 1/16W

PBUS Supply/Battery Charger

BATT_POS_GATE

SYNC_MASTER=RAYMOND

R7053



330K 5% MF-LF 402 1/16W


1K


5% 1/16W MF-LF 402 2


CHGR_VDD_R

DRAWING NUMBER

D APPLE INC.

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

8

8C2

7AMP

0.01

PPVBAT_G3H_CHGR_REG

2

TO SYSTEM

=PPBUS_G3H

F7000

R7008

CRITICAL

L7000

2

CRITICAL

1

R70731

1

1M

5% 1/16W MF-LF 402 2

Q7070

P

NOSTUFF D 6


PP18V5_S5_CHGR_SW_R CRITICAL CRITICAL

2


e r

1% 1/16W MF-LF 402 2

CHGR_AMON

1

CHGR_AMON 57D4 44B3 57A8 CHGR_BMON 44A6 =CHGR_ACOK 40D4

XW7000 SM

3.01K

AMON PULLDOWN LOGIC


0.5% 1W MF 2 0612


R7046

B

2

C7061 1 C7062

TRKL* 13 NC

1

57C6

CHGR_LGATE

10% 50V CERM 2 402

1

A

LGATE 21

0.001UF

GND_CHGR_SGND

57D5 57C6 8D1

CHGR_BOOT CHGR_UGATE CHGR_PHASE

R7020

CHGR_CSIN_XW7021

CHGR_BGATE CHGR_DCIN 57D8

BOOT 25 UGATE 24 PHASE 23

1CRITICAL

0.02

XW7021 SM

2

2

1

16 57A4 BGATE DCIN 2

5% 1/16W MF-LF 402

y r

a n i

CHGR_CSIP_XW7020

R7021 10 1

CHGR_AGATE CHGR_CSIP CHGR_CSIN

2

4

2

QFN

ICOMP VCOMP VNEG CSOP CSON

2

1

5 6 7 8

10% 16V X5R 402

0.033UF

CHGR_ICOMP 5 CHGR_VCOMP 7 CHGR_VNEG 8 CHGR_CSOP 18 CHGR_CSON 17

0.047UF

XW7020 SM

4

1

U7000

29 THRM_PAD

C7042

12 VHST AGATE 1 11 SCL 28 CRITICALCSIP 10 SDA CSIN 27 4 VREF 3 ACIN

C7024 1

VDDP

ISL6258A

NC CHGR_ACIN

57D4 57B5 44B3

1UF

10% 10V CERM 402

22 PGND

42B3

=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA

5% 1/16W MF-LF 402 1 2

C7040

10% 2 10V X5R 402-1

26 6 AGND

42C3

R7023 10

20

10% 10V 2 X5R 402-1

C

57C4 57B6

1

1UF

9.31K 1%

SOT23-5

CHGR_VDDP

5% 1/16W MF-LF 402

1UF 10%

10V X5R 402-1

C7047 1

R70111 1/16W MF-LF 402

=PP3V42_G3H_CHGR

2

R7040 4.7

U7060 TL331

1 2 3

57D5 57A8 8D1

2 CHGR_VDD 1

19

10% 25V 2 X5R 402

1

CHGR_LOWCURRENT_GATE

CRITICAL

2

1% 1/16W MF-LF 402 2

(CHGR_ACIN)

4

GND 3 CHGR_LOWCURRENT_REF

1.82K

0.1UF

62K

5% 1/16W MF-LF 402 2

5

1

CHGR_AMON

100K 5% 1/16W MF-LF 402

R7062 1

10% 25V X5R 402

2

1% 1/16W MF-LF 402 2

2 5% 1/16W MF-LF 402

C7010 1

0.1UF

R7060

R7001 62K

1

CHGR_LOWCURRENT_GATE_R 1

C7060

1

1

2

1/16W MF-LF 402 2

10% 25V 2 X5R 402

D R7099

1

100K 5%

0.1UF

=PP3V42_G3H_CHGR 57C6 57A8 8D1

1 2 3

R7098 1

1

G

C7063

4

SOD-723-HF

5 6 7 8

1SS418

2

D

1

D7010

S

D

2

1

3

8C1

A

OF 70

1

109

A

8

6

7

2

3

4

5

1

5V_RT/3.3V POWER SUPPLY D

D VOUT = (2 * RA / RB) + 2

ROUTING NOTE:

R7267 R7268 R7269 R7270 15.0K 10K 10K 6.49K

XW7203

Place XW7203 by Pin1 OF L7260.

SM 2

1% 1/16W MF-LF 402

5VRT_S0_VFB_XW7203

1

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

1

2

1

2

1

2

a n i

1

58A5

ROUTING NOTE:

XW7204

1% 1/16W MF-LF 402

GND_5VRT3V3S5_SGND

SM

3V3S5_VFB_R7270

2

Place XW7204 by Pin 2 of L7220.

2

1

XW7205 SM

2

C

=PPVIN_S0_5VRTS0 58B6 8C1

ROUTING NOTE:

XW7202

Place XW7202 by C7292.

1

SM 2

C7272 1UF 10%

2 25V X5R

1

603-1

m il

=PPVIN_S0_5VRTS0

5V3V3S5_REG3

8C1 58C6

10%

1

C7260

603-1

0.1UF 10%

5

16V X5R 402

CRITICAL

D

Q7260

2

SI7110DN PWRPK-1212-8-HF

B

8D6

L7260 1

2

VOLTAGE=5V

C7290 10UF 20%

2 6.3V X5R

603

C7291 150UF 20%

2 6.3V POLY-TANT

CASE-B2-SM

CRITICAL

1

Q7261 C7292 150UF

3 2 1

2

G

IN

2

D 6

9 4 3 2

21 DRVH1

19 DRVL1

U7200 QFN

24 VO1

2 VFB1

DRVH2 10 LL2 11

3V3S5_LL

DRVL2 12

1

EN0 13 GND THRM_PAD

1

C7273 10UF

20% 2 6.3V X5R 603

GND_5VRT3V3S5_SGND

CRITICAL

PWM FREQ. = 375 KHZ MAX CURRENT = 4A

L7220


Q1

10 SW

8

1

2

B

CRITICAL 4.7UH-5.5A

=PP3V3_S5_REG

IHLP2525CZ

1

1

R7272 57.6K 1%

2

C7252 150UF 20%

7 6 5

2 6.3V POLY-TANT

1/16W MF-LF 402

CASE-B2-SM

1

8B4

VOLTAGE=3.3V

CRITICAL

Q2

NC

NC


MLP


3V3S5_ENTRIP

PGOOD 23

R7271

2

CRITICAL

C7240 33UF

FDMS9600S

3V3S5VO2

ENTRIP2 6

1

Q7220

1

3V3S5DRVL

VO2 7

1 ENTRIP1

58C4

2

VFB2 5 3V3S5_VFB

VCLK 18

1/16W MF-LF 402

16V X5R 402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 3V3S5_DRVH

20 LL1

75K 1%

0.1UF 10%

3V3S5_VBST

5VRT_S0_DRVL

4

VREG5 17 5V3V3S5_REG5

C7241 1UF

10% 25V 2 X5R 603-1

C7220

22 VBST1 CRITICAL VBST2 9

5VRT_S0_LL

1

S

P =P5VRTS0_EN_L

64D1

A

G

SI7110DN

CASE-B2-SM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM 5VRT_S0_DRVH

5VRT_S0_ENTRIP

CRITICAL

20% PWRPK-1212-8-HF 2 6.3V POLY-TANT

5VRT_S0_VBST

5VRT_S0_VFB

D

CRITICAL 1

VREG3 8

4 TONSEL


1

603

VREF

C

8C1

2 6.3V X5R

VIN 14 SKIPSEL

5VRT_S0_VO1

5

IHLP

1

402

e r

3 2 1

CRITICAL 3.3UH

=PP5VRT_S0_REG

10%

2 10V CERM


S


4

G

1

C7271 0.22UF

3

C7281 1UF

2 25V X5R


25

C7280 33UF

1

10UF 20%

16

1

ROUTING NOTE:


=PPVIN_S5_3V3S5

C7270

1

CRITICAL

TPS51125

2

5VRTS3_3V3S5_VREF

15

1

y r

VOUT = (2 * RC / RD) + 2

CRITICAL 1

C7251 150UF

1

C7250 10UF 20%

20%

2 6.3V X5R

2 6.3V POLY-TANT

603

CASE-B2-SM

2

XW7201 SM

Q7221

SSM6N15FEAPE

P5V3V3_PGOOD 64A5

SOT563

ROUTING NOTE:

S 1

Q7221 D 3

Place XW7201 between Pin 15 and Pin 25 of U7200.

SSM6N15FEAPE

5V/3.3V SUPPLY

SOT563

SYNC_MASTER=RAYMOND

=P3V3S5_EN_L 5 64D6

IN

G

S 4


NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 72

1

109

A

8

6

7

2

3

4

5

1

1.5V/0.75V(DDR3) POWER SUPPLY D

402

=PPVTT_S3_DDR_BUF 27D3 8C4

1 1

2 1

10% 16V X5R 402

20% 2 6.3V X5R 603

1V5S3_V5FILT

2

1

C7300 1UF 10% 10V X5R 402-1

C7301 10UF

=PP5V_S3_1V5S30V75S0

2

1

R7307

a n i

8C3

C7302 10UF

4.7

5% 1/16W MF-LF 402

20% 6.3V X5R 603

2

1V5S3_VDDQSNS

1

8C8

R7310 10.7K

VDDQSET VTTREF VLDOIN VTT V5FILT

0

5% 1/16W MF-LF 402

VBST V5IN VDDQSNS VTTSNS

1% 1/16W MF-LF 2 402

1

=DDRVTT_EN

10 11

DRVH LL

TPS51116

COMP

QFN CS

ROUTING NOTE:

ROUTING NOTE:


C7308 22UF

20% 6.3V 2 X5R-CERM 603

19 1V5S3_DRVL

MODE

4

NC0 NC1

CS_GND

GND

PGND

VTTGND

5

C7309 0.1uF 10% 16V X5R 402

PWRPK-1212-8-HF

S

1 2 3

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.25 mm

5


D

SM-IHLP-1 1

CRITICAL

Q7321

7 NC 12 NC

4

2

C7330 33UF

CRITICAL

C7331 33UF

1


1


2

C7332

1

1UF 10%

2 25V X5R 603-1

C7333

0.001UF 20%

2

50V CERM 402

MAX CURRENT = 12A PWM FREQ. = 400 KHZ

CRITICAL L7320 1.0UH-13A-5.6M-OHM

G


1

SI7110DN

D

4

CRITICAL

CRITICAL

Q7320

=PP1V5_S3_REG


8D4

CRITICAL 1

CRITICAL

1

C7342 330UF

1

20% 2.5V 2 POLY-TANT CASE-D2E-SM PWRPK-1212-8-HF

SI7108DN

G

PUT ONE BULK CAP NEXT TO THE LOAD

VOLTAGE=1.5V

2

C

8C1

C7343 330UF

20% 2 2.5V POLY-TANT CASE-C2-SM1

C7341 10UF

20% 2 6.3V X5R 603

1

C7344 0.001UF

2

20% 50V CERM 402

1 2 3

e r

B

GND_1V5S3_SGND

ROUTING NOTE: PUT 6 VIAS UNDER THE THERMAL PAD

P

1

1

DDRREG_PGOOD

2

XW7300 SM

GND_1V5S3_CSGND

A

2

S

THRM_PAD

1

20% 6.3V 2 X5R-CERM 603

CRITICAL 1

25

C7307 22UF

2

21 1V5S3_DRVH 20 1V5S3_LL

DRVL

CONNECT CS_GND TO Q7321 PIN1,2.3 USING KEVIN CONNECTION.

18

16

3

1V5S3_CS

13

Place XW7301 by L7320.

=PPVIN_S5_1V5S30V75S0

m il

PGOOD

CRITICAL

17

SM

2

6

CRITICAL 1

S3 S5

U7300 SYM (1 OF 2) 1

=DDRREG_EN

XW7303

64C6

2

R7300

2

8

15

22

14

24

23

5

9 1

1

1V8S3_VBST_RC

1V5S3_VBST

ROUTING NOTE:

XW7301 SM

1V5S3_VTTSNS

=PP0V75_S0_REG

65A3 26C1

y r

50V CERM 402

0.1% 1/16W MF 402 2

C7340 0.033UF

1

C

D

VOUT = 0.75V * (1 + RA / RB) NO STUFF 1 2 1 2 1V5S3_VDDQSET R7322 C7303 20K 0.1% 100PF R7321 5% 1/16W MF 20K

R7399 100K

ROUTING NOTE:

Place XW7300 between Pin 3 and Pin 25 of U7300.

1

2

XW7302 SM

B 64A2

5% 1/16W MF-LF 402 2

=PP3V3_S3_PDCISENS

8D3

ROUTING NOTE:

Place XW7302 by Q7321.

STATE

PM_SLP_S4_L

PM_SLP_S3_L

PP1V5_S3

PP0V75_S0

S0

HIGH

HIGH

1.5V

0.75V

S3

HIGH

LOW

1.5V

0.0V

S5/G3HOT

LOW

LOW

0.0V

0.0V

1.5V/0.75V DDR3 SUPPLY SYNC_MASTER=RAYMOND



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 73

1

109

A

8

6

7

=PP5V_S0_CPU_IMVP

8D5

60D8 60C2 8C1

1

R7412

1

10

5% 1/16W MF-LF 402

D 60D4 60C2 8C1

2

1UF

10% 6.3V CERM 402 1

R7420

5% 1/16W MF-LF 402

PM_DPRSLPVR

IN

DPRSLPVR

10UF


C7496

1

0.01UF

10% 16V CERM 402

2

C7430 0.1uF

R7427

1

71A3 71A3

2 1

R7445

NO STUFF

C7410

499

ERT-J0EV474J

1% 1/16W MF-LF 2 402

0.01uF

1

C

IMVP6_NTC_R

71A3 71A3

2

NO STUFF

R7406

44B3

OUT

2 PSI* 3 IMON

IMVP6_IMON

1/16W MF-LF

CPU_PROCHOT_L 402 1

(NC)

2

FROM SMC 1

39C8 26A8

2

OUT

IMVP6_VR_TT IMVP6_NTC

R7408

C7405

147K 1%

0.015uF

IMVP_VR_ON VR_PWRGOOD_DELAY

IN

1/16W MF-LF 402

10% 16V X7R 402

1

60A4

2

60A4

IMVP6_SOFT

IMVP6_VDIFF

34

IMVP6_PHASE1

32 60A8 LGATE1 33

IMVP6_LGATE1 (GND)

24

IMVP6_ISEN1

60A8 PHASE1

PGND1 60A8 ISEN1

IMVP6_LGATE2 (GND)

1

R7409

2

1K

1% 1/16W MF-LF 2 402

1

0.001UF

10% 50V CERM 402

IMVP6_FB2 IMVP6_FB 60A4 IMVP6_COMP 60A4 IMVP6_VW

2

60A4

NO STUFF

60A4

R7413

1K

IMVP6_VDIFF_RC 1

R7411

1% 1/16W MF-LF 402

60A4 VO

12 FB2 11 FB

VSEN

10 COMP 9 VW

RTN

VOLTAGE=0V

2

C7413 220PF

1

5% 25V CERM 402

2

R7414

C7407

0.001UF

10% 50V CERM 402

97.6K (IMVP6_COMP)

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

1

C7431

R7410

1

6.81K

P OMIT

m il

1% 1/16W MF-LF 2 402

0.068UF

10% 10V CERM 402

2

60A4

5.36K

1% 1/16W MF-LF 402

1

180pF

5% 2 50V CERM 402

60C6 60C6 60C6 60C6 60C6

IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1

60C6 60C6 60C6 60C6 60C6

1

1

2

R7416

10% 50V CERM 402

C7401 33UF

1


C7428

2

10% 10.0V CERM-X5R 2 402

10% 6.3V CERM-X5R 402

2

1

10% 6.3V CERM-X5R 402

5% 1/16W MF-LF 2 402

IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2

=PPVCORE_S0_CPU_REG

2

8D8

1 1

5

1 2

1 C7408 33UF

20% 16V 2 POLY-TANT CASED2E-SM

C7411 1

1UF

10% 25V X5R 603-1

2

1/16W MF-LF 402

2

1

C7403

2

R7404

1

0.22uF

5% 1/16W MF-LF 402

10% 6.3V CERM-X5R 402

0.12UF

1

0.22UF

R7415 11K

1% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

IMVP6_VO_R

1

1

2

CRITICAL

R7431

C

C7422

0.001UF 20% 50V CERM 402

RJK0305DPB LFPAK-HF (IMVP6_PHASE2)

1

R7401 3.65K

1% 1/16W MF-LF 2 402

1

L7401

CRITICAL

1

0.36UH-30A-0.80MOHM MPC1055-SM

MPC1055LR36 DCR=0.8MOHM

RJK0328DPB

4

2

CRITICAL

Q7403

2

1

1

2

R7405

10K

1

20% 50V CERM 402

2

R7407

1

0.22uF

1% 1/16W MF-LF 402

1 2 3

2

C7404

5% 1/16W MF-LF 402

10% 6.3V CERM-X5R 402

B

NO STUFF 2

NO STUFF

1

C7402

1

0.0022UF

R7452 10K

R7443 3.65K

10% 50V CERM 402

1% 1/16W MF-LF 402

1% 1/16W MF-LF 2 402

10KOHM-5%

(IMVP6_ISEN2)

0603-LF

2

(IMVP6_VSUM)

ERT-J1VR103J

(IMVP6_VO)

R7423 0

1

R7422 0

5% 1/16W MF-LF 2 402

CPU_VCCSENSE_P CPU_VCCSENSE_N

11A5 71A3 11A5 71A3

60B6 60C6 60C8 60B7 60B6 60B6 60B6 60C7 60B7

MIN_LINE_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

MIN_NECK_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

60B7 60B7 60B7 60B7 60B7

IMVP6_OCSET IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

MIN_LINE_WIDTH 0.25 MM 0.25 MM 0.50 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

MIN_NECK_WIDTH 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.20 MM 0.25 MM

IMVP6 CPU VCore Regulator SYNC_MASTER=RAYMOND

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

IMVP6_RTN IMVP6_VSEN

0.25 MM 0.25 MM

0.25 MM 0.25 MM

DRAWING NUMBER

D APPLE INC.

4

3

2

REV.

051-7537

SCALE

SHT NONE

5



SIZE

6

C7423 0.001UF

LFPAK-HF

R7430

60B5

7

20% 50V CERM 402

2

NO STUFF R7451 10K 1%

8C1 60D4 60D8

1% 1/16W MF-LF 2 402

60B6

8

C7420 0.001UF

2

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

2

C7421 0.22uF

1

R7400

10K

1% 1/16W MF-LF 402

3.92K

C7434 1

0.018UF

1

D

Q7402

1 2 3

10% 16V X7R 402

2

1

2

CRITICAL

13.7K

1

IMVP6 CPU VCORE REGULATOR MIN_NECK_WIDTH 0.25 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

10% 50V CERM 402

C7429

1

C7433

XW7400 SM

MIN_LINE_WIDTH 1.5 MM 0.25 MM 1.5 MM 1.5 MM 0.25 MM

C7400

0.0022UF

1

(IMVP6_VO)

10% 16V CERM 402

1% 1/16W MF-LF 2 402

1

2

R7418 R7417

0.01UF

(IMVP6_VW)

1

NO STUFF

C7416

C7432

IMVP6_COMP_RC

A

49

1

GND_IMVP6_SGND

a n i

0.1UF

10% 16V 2 X5R 402

10% 16V X5R 402

1

MPC1055-SM

1 2 3

C7415

NO STUFF

NO STUFF

10% 50V CERM 402

1% 1/16W MF-LF 2 402

2


MPC1055LR36 DCR=0.8MOHM

RJK0328DPB

5

1K

1

20% 50V CERM 402

0.36UH-30A-0.80MOHM

Q7401

4

1

15

60A4

470PF

1

0.1UF

1

14

TPAD

21

C7414

1

IMVP6_DFB

2

L7400

=PPVIN_S5_CPU_IMVP CRITICAL CRITICAL

e r GND

60A4 60C8

2

17

18

25 NC

(IMVP6_FB)

C7427

0.001UF

1% 1/16W MF-LF 2 402

1

16

IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP

20% 16V POLY-TANT 2 CASED2E-SM

C7419

0.001UF

CRITICAL

CRITICAL

2

IMVP6_ISEN2

60A4

1

1UF

(IMVP6_PHASE1) 1-PHASE DCM

2

19

255

B

29

C7418

10% 25V X5R 603-1

y r

1 2 3

1-PHASE DCM

LFPAK-HF

2

2

1

LOAD LINE SLOPE = -2.1 MV/A

IMVP6_UGATE2 IMVP6_PHASE2

60A4 DFB

C7406

1


C7417 33UF

LFPAK-HF

4

1

CRITICAL 1

(IMVP6_ISEN1)

60A6 30 LGATE2

60A4 DROOP 60A4

5% 1/16W MF-LF 402

60A6 28 PHASE2

60A4 VSUM OCSET 8

7 SOFT

13 VDIFF

IMVP6_UGATE1

60A6 23 ISEN2

6 NTC

4 RBIAS

35

PGND2

1 PGOOD 5 VR_TT*

IMVP6_RBIAS

26

60A8 UGATE1

60A6 27 UGATE2

48 3V3 47 CLK_EN* 44 VR_ON

0

IMVP6_BOOT1 IMVP6_BOOT2

QFN

46 DPRSTP* 45 DPRSLPVR

0 5% 71B3 40D4 14B6 10C5

C7409 33UF

1-PHASE CCM

IMVP6_BOOT1_RC

2

R7425

U7400BOOT2

38 VID1 37 VID0

IN

31 PVCC

CRITICAL60A6

41 VID4 40 VID3 39 VID2

CPU_DPRSTP_L 71B3 IMVP_DPRSLPVR 10A2 IN CPU_PSI_L

71B3 14A3 10B2 9B2

VDD

60A8 36 BOOT1

43 VID6 42 VID5

CPU_VID 11B6 CPU_VID 11B6 CPU_VID 11B6 CPU_VID 71A3 11B6 CPU_VID 71A3 11B6 CPU_VID 11B6 CPU_VID

71A3 11B6

CRITICAL

1

22

20 VIN

R7426

2

10% 16V CERM 402

5% 1/16W MF-LF

2

2 402

470K 402

2

RJK0305DPB

2-PHASE CCM

5% 1/16W MF-LF 402 1 2 IMVP6_BOOT2_RC

2.0K

NO STUFF

4.02K

1% 1/16W MF-LF 402

1 0 1 0

R7424

R7447

1

10% 16V X5R 402

5% 1/16W MF-LF 402

Q7400

4

0

1

IMVP6_VSEN

GND_IMVP6_SGND NO STUFF

1

IMVP6_RTN

R7421

10

60B7 60A4

OPERATION MODE

PP3V3_S0_IMVP6_3V3

2

1

CRITICAL

5

ISL9504BCRZ

=PP3V3_S0_IMVP1

PSI*

1 1 0 0

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 8C5

DPRSTP*

0 0 1 1

20% 6.3V X5R 603

PPVIN_S5_IMVP6_VIN

2

10

71B3 21C7

C7435

1

2

=PPVIN_S5_CPU_IMVP

CRITICAL

5

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

C7426

1

=PPVIN_S5_CPU_IMVP

PP5V_S0_IMVP6_VDD

2

2

3

4

5

A

OF 74

1

109

A

8

6

7

2

3

4

5

1

MCP VCORE/5V_S3 LEFT REGULATOR

D

y r

=PPVIN_S3_5VLTS3 8C1

VOLTAGE=12.6V MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

CRITICAL

C7512

1

0.001UF 20% 50V CERM 402

2

Q7510

5

SI7110DN PWRPK-1212-8-HF

D

PP5V_S3_MCPREG_LDO

4

G

61C5 8C1

S 1

1


2

C7510

3 2 1

C7511

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

10% 25V X5R 603-1

C7500

CRITICAL

Q7511

1

C7501

10UF

1UF

10% 25V X5R 805

10% 6.3V CERM 402

2

CRITICAL


MCPREG_VREF3

SI7110DN

5

PWRPK-1212-8-HF

5

C7504 D

(P5VLTS3_LGATE)

L7520 3.3UH

=PP5VLT_S3_REG 8C4

FREQ = 400 KHZ

1

C7514 0.1UF

2

2

10% 50V X7R 603-1

P5VLTS3_BOOT P5VLTS3_UGATE P5VLTS3_PHASE P5VLTS3_LGATE

(P5VLTS3_PHASE) MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

IHLP

(=PP5VLT_S3_REG) (=P5VLTS3_EN) 1

2

C7516 10UF

2

20% 10V X5R 805

XW7501 SM

PLACEMENT_NOTE=Place next to C7516

CRITICAL 1

2

1

1

P5VLTS3_VSNS

150UF

C7518

20% 2 6.3V POLY-TANT CASE-B2-SM

0.001UF 20% 50V CERM 402

NO STUFF 1

R7521 61.9K

1% 1/16W MF-LF 2 402

CRITICAL

C7517

NO STUFF

C7520 100PF 5% 50V CERM 402

180K

R7522

5% 1/16W MF-LF 402

0

2

5% 1/16W MF-LF 402

2

Vout = 0.7V * (1 + Ra / Rb) 64B6

IN

64A5

OUT

64A5

OUT

64C1

21C3 21A3

IN

IN

21C3 21A3

IN

21C3 21A3

IN

=P5VLTS3_EN MCPCORES0_PGOOD P5V_LT_S3_PGOOD =MCPCORES0_EN


5

3

U7500

7 8 24 26 25 23 30 27

61C6

Max load 100mA PP5V_S3_MCPREG_LDO

A

QTY

2

P

DESCRIPTION

REFERENCE DES

CRITICAL

(MCPCORES0_UGATE)

4.7UF

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE

20% 6.3V X5R-CERM 402

SM

PP2V_S0_MCPREG_REF

Max load 50uA

1

2

20% 10V CERM 402

0.001UF 20% 50V CERM 402

1UF

10% 25V X5R 603-1

2

2

CRITICAL

Q7560

Vout = See below Max Current: 25A? (Q7560 Limit) FREQ = 300 KHZ

RJK0305DPB LFPAK-HF

1

2

C

CRITICAL

3

L7500 =PPMCPCORE_S0_REG

0.6UH-30A-1.5MOHM 1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE

MPL104-SM

C7566 20% 4V X5R 603

Q7565

4

1

2

1

10UF CRITICAL RJK0328DPB

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE

R7570 1

8C8

2

5

(MCPCORES0_LGATE)

1

LFPAK-HF

C7567

CRITICAL 1

0.001UF 20% 50V CERM 402

10UF 2

2

C7570

20% 4V X5R 603

1

C7565

C7569 0.0027UF

330UF 20% 2 2.5V POLY-TANT CASE-C2-SM

2

10% 50V CERM 402

3

48.7K

0.1% 1/16W MF 402 2

R7530 1

C7530

C7562

1

C7561

MCP_PROD

0.1UF

2

1


2

44D8 77D3

VOLTAGE=2V

1

33UF

(MCPCORES0_PHASE)

MCPCORES0_REFIN MCPCORES0_ILIM

1

C7560

1

0.22UF

MCP_PROD

XW7500

4

5% 10V CERM-X7R 603

m il VREF2 1 PGOOD1 13 PGOOD2 28

C7502

C7564

VOLTAGE=5V

R7571

MCP_PROD

1

1

MCP_PROD 1

R7580

MCP_PROD 1

R7581

R7582

180K

54.9K

475K

237K

110K

5% 1/16W MF-LF 402

0.1% 1/16W MF 402

0.1% 1/16W MF 402

0.1% 1/16W MF 402

0.1% 1/16W MF 402

2

2

2

GND_MCPREG_SGND

2

2

MCP_VID0_L


B PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.

MCP_VID1_L

MCP_VID2_L

Q7582 Q7580

Vout = 2.0V * Req / (Ra + Req)

D

3

Q7580

SSM6N15FEAPE

SSM6N15FEAPE

SOT563

SOT563

D

SSM3K15FV

6

D 3 =PPVCORE_S0_MCP

SOD-VESM-HF

8C8 22D5 24D8 44D7

Req = Rb || Rc || Rd || Re

5

G

S

2

4

G

S

1

1

G

CRITICAL

S 2

C7568 330UF

R7590 1

7.5K

2

5% 1/16W MF-LF 402

R7591 1

1

7.5K

7.5K

2

C7590

2

5% 1/16W MF-LF 402

BOM OPTION

114S0383

1

RES,MTL FILM,1/16W,49.9K,1,0402,SMD,LF

R7570

MCP_A01

114S0401

1


R7571

MCP_A01

114S0484

1

RES,MTL FILM,1/16W,549K,1,0402,SMD,LF

R7580

MCP_A01

114S0454

1


R7581

MCP_A01

114S0423

1


R7582

MCP_A01

114S0373

1


R7570

MCP_A01P&MCP_A01Q

114S0404

1


R7571

MCP_A01P&MCP_A01Q

001 010

+1.159V +1.101V

+0.994V +0.937V

+1.00V +0.95V

114S0458

1


R7580

MCP_A01P&MCP_A01Q

011

+1.049V

+0.885V

+0.90V

Rev A01 VID 000

Voltage +1.224V

+1.060V

C7591

1

1

C7592

0.1UF

0.1UF

0.1UF

20% 10V CERM 402

20% 10V CERM 402

20% 10V CERM 402

2

2

1

C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE 2

M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:

Production Voltage

20% 2.5V POLY-TANT CASE-C2-SM

MCP_VID0_RC MCP_VID1_RC MCP_VID2_RC

5% 1/16W MF-LF 402

R7592

MCP79 Rev A01 requires higher core & analog voltage PART NUMBER

10% 6.3V CERM 402

(SGND) MCPCORES0_BOOT MCPCORES0_UGATE MCPCORES0_PHASE MCPCORES0_LGATE ISNS_PVCORES0MCP_N REGULATE TO AFTER SENSE RES

REFIN2 32 TRIP2 31

e r

R7520 1 1

LDO LDOREFIN VBST2 CRITICAL DRVH2 LL2 QFN DRVL2 VOUT2 EN2

2

1 20% 2 6.3V POLY-TANT CASE-B2-SM

1

THRM_PAD GND PGND

1

150UF

B

61C5

(=P5VLTS3_EN) PP5V_S0_MCPREG_VCC

VIN VBST1 DRVH1 LL1 DRVL1 VOUT1 EN1 VSW VFB1 TRIP1 SKIPSEL EN_LDO V5DRV1 TONSEL

33

C7515

P5VLTS3_FB P5VLTS3_ILIM

6 17 15 16 18 10 14 9 11 12 29 4 20 2

C7503 1UF

VREF3

1

2

22

CRITICAL

V5FILT

(P5VLTS3_BOOT) MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

3 2 1

7A MAX OUTPUT VOUT = 5V

SN0802043

(Q7510 LIMIT)

21

C

S

10% 6.3V CERM 402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

19

G

4

1

1UF

V5DRV

PWRPK-1212-8-HF

=PPVIN_S0_MCPCORES0

8C1

(Internal 10-ohm path from PVCC to VCC) 61B6 PP5V_S0_MCPREG_VCC

(P5VLTS3_UGATE)

1UF

33UF

a n i

=PPVIN_S0_MCPREG_VIN

CRITICAL

D

MCP Target +1.05V

MCP VCORE REGULATOR

Added C7568 bulk cap on output. Tied TON to REF. Changed Q7510 to 376S0674. C7500 changed to 138S0638. L7560 changed from T18 MLB inductor to 152S0782. Changed Q7565 to 376S0637. Changed R7514 to 280K, R7564 to 180K.

SYNC_MASTER=RAYMOND



114S0447

1


R7581

MCP_A01P&MCP_A01Q

100

+0.995V

+0.830V

+0.85V

114S0411

1


R7582

MCP_A01P&MCP_A01Q

101

+0.952V

+0.789V

+0.80V

110

+0.913V

+0.752V

+0.75V


APPLE INC.

111

8

7

6

5

+0.876V

+0.719V

4

DRAWING NUMBER

D

+0.70V

SCALE

SHT NONE

3

2

REV.

051-7537

A

OF 75

1

109

A

8

6

7

2

3

4

5

1

CPUVTT POWER SUPPLY

D

8C1

CRITICAL 1

1


C7695 1UF

33UF 2

2

10% 25V X5R 603-1

1

C7696 0.001UF 20% 50V CERM 402

2

5

C

y r

a n i

=PPVIN_S0_CPUVTTS0

C7630

D

D

CRITICAL

Q7620

C

SI7110DN

4

G

PWRPK-1212-8-HF

S 8D5

R7601

R7603

C7601

1

1UF 10% 10V X5R 402-1

V5FILT 2

1

C7604 4.7UF

V5DRV 2

CRITICAL

10% 6.3V X5R-CERM 603

U7600 64C1

64A5

IN

=CPUVTTS0_EN

1

OUT

CPUVTTS0_PGOOD

6

PGOOD

3

VOUT

5

VFB

VBST

2

CPUVTTS0_TON

14

CPUVTTS0_VBST

DRVH

13

LL

12

CPUVTTS0_DRVH GATE_NODE=TRUE

CPUVTTS0_VFB

CPUVTTS0_LL

e r SWITCH_NODE=TRUE

CPUVTTS0_TRIP

11

TRIP

DRVL

9

CPUVTTS0_DRVL

GATE_NODE=TRUE

R7604 6.65K

1% 1/16W MF-LF 2 402

PGND 8

7

B

1

THRM_PAD 15

GND

XW7600 SM

1

2

(GND)

ROUTING NOTE:

P

CPUVTTS0_VOUT

A

5

187K 1% 1/16W MF-LF 402

D

2

4

TPS51117RGY_QFN14 SYM QFN (2 OF 2) EN_PSV TON

(=PPCPUVTT_S0_REG)

1

C7603

G

1

S

0.1UF


10% 50V X7R 603-1

1

SM-IHLP-1

2

XW7665 SM

CRITICAL

1

Q7621

SI7108DN

1 2 3

2

PWRPK-1212-8-HF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

CPUVTTS0_VSNS


Place XW7600 between Pin 7 and Pin 15 of U7600. GND_CPUVTTS0_SGND

1

NO STUFF

R7670 8.45K

1% 1/16W MF-LF 2 402

C7670

1

100PF 5% 50V CERM 402

2

1

R7671

1

C7665 10UF

2

8D8 65A6

Vout = 1.052V 8A max output F = 400 KHZ

1

20% 6.3V X5R 603

2

CRITICAL

C7660

C7661

0.001UF 20% 50V CERM 402

1

330UF 20% 2.5V 2 POLY-TANT CASE-C2-SM

B 2

XW7601

SM

m il

PP5V_S0_CPUVTTS0_V5FILT MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

10

1% 1/16W MF-LF 402

2

4

301

1.0UH-13A-5.6M-OHM 2 CRITICAL PLACEMENT_NOTE=Place XW7665 next to L7620

1

=PPCPUVTT_S0_REG

L7620

1 2 3

=PP5V_S0_CPUVTTS0

1

20.0K 1% 1/16W MF-LF 2 402

ROUTING NOTE:



Vout = 0.75V * (1 + Ra / Rb)

(CPUVTTS0_VFB)

(=PPCPUVTT_S0_REG)

CPU VTT(1.05V) SUPPLY SYNC_MASTER=RAYMOND



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 76

1

109

A

8

6

7

2

3

4

5

1

D

D

y r

1.8V S0 SWITCHER

a n i

INPUT RAIL IS 3.3V S0 8B5

=PPVIN_S0_P1V8S0

CRITICAL

1

C

VI

C7760

1

10uF 20% 6.3V X5R 603

U7760

TPS62202

2

4

64C1

=P1V8S0_EN

3

FB EN

SW 5

2

m il

=PP3V3_S5_P1V05S5 8A3

1

5% 1/16W MF-LF 402

2

1

B

2

e r

CRITICAL

R7722

1

C7720 22UF

20% 6.3V CERM 805

2.2UH-3.25A IHLP1616BZ-SM

AVINPVIN

=P1V05_S5_EN

6

64D6

5

CRITICAL SW

EN OVT

U7750FB TPS62510

P

C7781

7

MODE

PG

BQA

402

1V05S5_SGND

11

3

0.1UF 10%

2 16V X5R

2

AGND PGND THRM_PAD

1

CRITICAL

L7720

10

9

1V05S5_AVIN

1 1V05S5_SW

1

2

4 1V05S5_FB 8

2 50V CERM

402

P1V05_S5_PGOOD

PCAA031B-SM

P1V8S0_SW

1

MAX CURRENT = 200MA

=PP1V8_S0_REG

2

C7762 10uF 20% 6.3V X5R 603

2

B

8B4

1

2 1

MCP_PROD

64B1

2

VOUT = 0.6V * (1 + Ra / Rb)

1% 1/16W MF-LF 402

1

2 R7781 392K 1% 1/16W MF-LF 402 1

Vout = 1.05V

CRITICAL

MAX Current = 1.5A

C7783 22UF

FREQ = 1Mhz

20% 6.3V CERM 805

2

XW7700 SM

MISC POWER SUPPLIES

MCP79 Rev A01 requires higher voltage

A

PART NUMBER VOUT = 1.102V

114S0464

QTY 1

DESCRIPTION

RES,MTL FILM,1/16W,348K,1%,0402,SMD,LF

8B8

1

=PP1V05_S5_REG

1 C7782 R7780 22PF 301K 5%

C

L7760

10UH-0.55A-330MOHM

SOT23-5

GND

MCP 1.05V_S5 AUXC SUPPLY

CRITICAL

REFERENCE DES

CRITICAL

R7781

SYNC_MASTER=RAYMOND

BOM OPTION





DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 77

1

109

A

8

6

7

2

3

4

5

1

3.3V 1.05V S5 ENABLE

Power Control Signals

R7802 64D3 64B3 8D1

100K

2

=PP3V42_G3H_PWRCTL

1

PM_G2_P3V3S5_EN_L

=P3V3S5_EN_L

OUT

3.3V_S0, 1.8V_S0 ENABLE MCPDDR, CPUVTT,MCPCORES0 ENABLE 1.5V S0 AND 1.05V S0 ENABLE

58A5

MAKE_BASE=TRUE

5% 1/16W MF-LF 402

1

D

2

D 3

PM_SLP_S3_L

Run (S0)

1

1

1

Sleep (S3)

1

1

0

Soft-Off (S5)

1

0

0

10% 10V CERM

SMC_PM_G2_EN

IN

PM_SLP_S4_L

D

402

SOD-VESM-HF

39D5 7C3

SMC_PM_G2_ENABLE

C7802 0.068UF

Q7800 SSM3K15FV

State

NO STUFF

0

Battery Off (G3Hot)

R7813 64D8 64B3 8D1

0

0

=PP3V42_G3H_PWRCTL

68K

2

1

100K 5% 1/16W MF-LF 402

y r

1

5%

1

R7800

G

1/16W MF-LF 402

S 2

Q7813

D 3

2

2

5.1K

1 PM_G2_P1V05S5_EN

OUT

63B7

68D8 41A5 39C5 34B7 21C3 7C3

C7801

IN

G

1

PM_SLP_S3_L

S 2

(PM_SLP_S3_L)

10% 6.3V CERM-X5R 402

NO STUFF

R7879

C7858

64B3 8A3 =PP3V3_S5_PWRCTL

1

0.1UF

5% 1/16W MF-LF 402

a n i

2

100K

2

5 2

1

B

R7881

2

5% 1/16W MF-LF 402

1

3

22K

4 (PM_SLP_S3_L_BUF)

R7882

2

5% 1/16W MF-LF 402

1

1


R7883

2

5% 1/16W MF-LF 402

33K

1

5.1K

=P3V3S0_EN

OUT

65B8

=PBUSVSENS_EN

OUT

43B7

R7884

2

5% 1/16W MF-LF 402

0

CERM

5% 1/16W MF-LF 402

1

0

P1V05S0_EN

P1V8S0_EN

PM_SLP_S4_L

(PM_S4_STATE_L)

MAKE_BASE=TRUE

=P3V3S3_EN

OUT

65C8

MCPDDR_EN

1

2 10% 6.3V CERM-X5R 402

2

1

OUT

59B8

=USB_PWR_EN

OUT

37B7

1

m il

0.47UF 2

2 10% 6.3V CERM-X5R 402

P5VLTS3_EN

=P5VLTS3_EN

MAKE_BASE=TRUE

OUT

61B8

e r

B

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

8B5 =PP3V3_S0_VMON

P C7870

1

0.1uF

3

20% 10V CERM 402

VCC

U7870 LTC2909

NC =PP1V05_S0_VMON

SEL

8 7

ADJ1 ADJ2

6

REF

DFN

RST*

GND 5

A

TMR

2 4

2

C7880

1

0.47UF

2

10% 6.3V

CERM-X5R

C7881

1

0.47UF

2

402

10% 6.3V

CERM-X5R

1

C7882

=CPUVTTS0_EN

OUT

62B7

=MCPCORES0_EN

OUT

61B8

2

10% 6.3V

2

CERM-X5R 402

402

C

NO STUFF

1

C7883

0.47UF

0.47UF

C7884 0.47UF

10% 6.3V

2

CERM-X5R 402

10% 6.3V CERM-X5R 402

VOLTAGE MONITOR

64D8 64D3 8D1 =PP3V42_G3H_PWRCTL

64C4 8A3

=PP3V3_S5_PWRCTL

C7840

1 1

0.1uF 20% 10V CERM 402

5 SENSE

U7840

B

R7840 100K

2

6 VDD

2

RESET* 1

5% 1/16W MF-LF 402

RSMRST_PWRGD

39D8

P1V05_S5_PGOOD

63A6

TPS3808G33DBVRG4 CT

4 CT

SOT23-6

MR* 3

TPS3808 MR* HAS INTERNAL PULLUP

GND

C7841

1

0.001UF 20% 50V CERM 402

OTHER S0 RAILS PGOOD

2

8B5 =PP3V3_S0_PWRCTL

TIE TMR TO GND TRST = 200MS

R7820

1

10K 5% 1/16W MF-LF 402

S0PGOOD_PWROK

2

POWER SEQUENCING

Unused PGOOD signal

THRM_PAD

58A2

P5V3V3_PGOOD

IN

TP_DDRREG_PGOOD

9

=PP1V5_S0_VMON

1

MCPCORES0_EN

1

NO STUFF

=DDRREG_EN

C7812

5% 1/16W MF-LF 402

65C4

MAKE_BASE=TRUE

NO STUFF

1

100 5%

MAKE_BASE=TRUE

0

OUT

MAKE_BASE=TRUE

1/16W MF-LF 402

DDRREG_EN

R7812

CPUVTTS0_EN

R7859

2

2 5% 1/16W MF-LF 402

63C4

=MCPDDR_EN

MAKE_BASE=TRUE

0.47UF

5.1K 1

100K 5% 1/16W MF-LF 402

R7811

1

65A8

OUT

2

R7810

OUT

=P1V8S0_EN

MAKE_BASE=TRUE

C7810

8B7

R7880

2

SOT665

S3 ENABLE

8B7

MAKE_BASE=TRUE

TC7SZ08AFEAPE

A

U7859 Y (PM_SLP_S3_L)

PM_SLP_S3_L_BUF

1

20% 10V CERM 402

NO STUFF

C

10% 10V 402

0.47UF

IN

58A7

C7813

2

2

OUT

NO STUFF 0.068UF

=P1V05_S5_EN

MAKE_BASE=TRUE

1

=P5VRTS0_EN_L

MAKE_BASE=TRUE

SOD-VESM-HF

1

5% 1/16W MF-LF 402

40A2 39C5 21C3 7C3

PM_SLP_S3_L_INVERT

SSM3K15FV

R7801

DDRREG_PGOOD

59B3

SYNC_MASTER=YUAN.MA


MAKE_BASE=TRUE 61B8

MCPCORES0_PGOOD

IN

LTC2909 THRESHOLD IS 95% (3.136V) 1.5V 1.05V COMPARED TO 0.5V 62B7


CPUVTTS0_PGOOD

IN

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 61B8


P5V_LT_S3_PGOOD

IN

ALL_SYS_PWRGD

OUT


26A8 39D8

MAKE_BASE=TRUE

SIZE

(S0PGOOD_PWROK)

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 78

1

109

A

8

6

7

5

2

3

4

1

1.5V S0 FET 3.3V S3 FET (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

CRITICAL

Q7910 FDC638P_G

3.3V S3 FET

SM

=PP3V3_S3_FET

8D4

=PP3V3_S5_P3V3S3FET

8A3

6

D

5

MOSFET

FDC638P

CHANNEL

P-TYPE

=PP1V5_S3_P1V5S0FET

8D3

D

4 2

R7912

C7911

1

1

10K

RDS(ON)

10% 16V

5% 1/16W

402

3

402 2

1

P3V3S3_SS

2

8C3

Q7903 SSM3K15FV

y r 20% 10V CERM 402

R7901

=PP5V_S3_MCPDDRFET

1

2

10%

MF-LF

16V

402

CERM

R7903

402

D 3

10K

1

5% 1/16W MF-LF 402

64C6

IN

G

Q7971

2

D

47K

1

3

SOT563

3.3V S0 FET

64C1

CRITICAL

Q7930

C

FDC606P_G

5%

402

2

X5R

MF-LF

26 MOHM @4.5V

LOADING

1.431 A (EDP)

1

P3V3S0_SS

2

2

5% 10%

1/16W

Q7905

16V

MF-LF

CERM

402

SSM3K15FV

402

D 3

SOD-VESM-HF

1 64C1

IN

G

S 2

=P3V3S0_EN

1.05V S0 FET 8B3

NO STUFF 8C3

1

220K 2

P1V05S0_SS

2

1

D

R7954

0.1UF =PP3V3_S5_P1V05FET

SOT6-HF

NO STUFF

C7952

8A3

P1V05S0_RC 1

R7953

3

2

NO STUFF

SSM6N15FEAPE SOT563

NO STUFF

2

R7951 P1V05_EN_L

A

1

100K 2

D

Q7951

D

3

SSM6N15FEAPE

S

6

1

=PPVTT_S0_VTTCLAMP

2

FDC655BN

CHANNEL

N-TYPE

RDS(ON)

30 MOHM @4.0V VGS

6

LOADING

1.1A (EDP)

=PP1V05_S0_FET

2

G

S

1

1

8C3

10% 10V CERM 402

1.5V S0 FET MOSFET

SI7108DNS

CHANNEL

N-TYPE

MCPDDR_EN_L_RC

RDS(ON)

6 MOHM @3.5V VGS

LOADING

5A (EDP)

C

B

10

1

VTTCLAMP_L

90mA max load @ 0.9V 81mW max power CKT FROM T18 6

S

1

SOT563

100K 5% 1/16W MF-LF 402

D

SSM6N15FEAPE

R7976 1

2

2

G

VTTCLAMP_EN

8C8

Q7975

D

3

NO STUFF

C7976

SSM6N15FEAPE

20% 50V CERM 402

1

R7955

5

0 5%

59C8 26C1

1/8W

IN

G

1

0.001UF

SOT563

S

POWER FETS

2

SYNC_MASTER=YUAN.MA


4


=DDRVTT_EN

MF-LF 805

SOT563

C7903 0.068UF

2

Q7975

0.068UF

P1V05_EN_L_RC

1

1

=PP5V_S3_VTTCLAMP

C7953 10% 10V CERM 402

S

5% 1/10W MF-LF 603

2 5

G

2

8B8

R7975 8C7

NO STUFF

2

5% 1/16W MF-LF 402

NO STUFF

G

4

Q7951

1

10K 5% 1/16W MF-LF 402

510 5% 1/16W MF-LF 402

20% 10V CERM 402

NO STUFF

MOSFET

2

=PP1V5_S0_FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT NVIDIA RECOMMENDS UNPOWERING DURING SLEEP. IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW BEFORE RAIL IS TURNED OFF, AND REMAINS LOW UNTIL AFTER RAIL TURNS BACK ON OR DIMMS WILL EXIT SELF-REFRESH PREMATURELY. MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS LOW THROUGH VTT TERMINATION RESISTORS.

1.05V S0 FET

Q7953

4

FDC655BN_G

5% 1/16W MF-LF 402

NO STUFF

P

NO STUFF CRITICAL

R7952

=PP5V_S3_P1V05S0FET

=PP1V05_S5_P1V05S0FET

2 3

MCP79 DDRVTT FET

e r

B

S

=MCPDDR_EN

m il

0.01UF

47K 1

P-TYPE

RDS(ON)

C7930

R7930 P3V3S0_EN_L

2

D

402 2

FDC606P

CHANNEL

G

10% 16V

1/16W

MOSFET

1

0.033UF

100K

8C6

3

R7932

C7931

1

3.3V S0 FET

=PP3V3_S0_FET

1

S

=PP3V3_S5_P3V3S0FET

4

8A3

5 6

SOT-6

IN

G

1

5% 1/16W MF-LF 402

SSM6N15FEAPE

5

PWRPK-1212-8-HF

6

SOT563

MCPDDR_EN_L

=P3V3S3_EN

D

Q7971

a n i

S 2

SI7108DN

SSM6N15FEAPE

R7971

1

G

CRITICAL

Q7901

S

100K

SOD-VESM-HF

D

2

4

MCPDDR_SS

2

5% 1/16W MF-LF 402

5% 1/16W

5

1

0.1UF

0.182 A (EDP)

0.01UF

47K 1

LOADING

C7910

R7910 P3V3S3_EN_L

48 mOhm @4.5V

2

X5R

MF-LF

C7902

1

0.033UF


2

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 5

64C1

IN

G

S

4


P1V05S0_EN 62C2 8D8

=PPCPUVTT_S0_REG

SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

.

REV.

051-7537

A

OF 79

1

109

A

8

6

7

2

3

4

5

1

D

D

y r LCD

a n i C9015

0.001UF 10% 50V X7R

L9004

8A3

Q9003

=PP3V3_S5_LCD 4

R9023

LCDVDD_PWREN_L 1

Q9004

SSM3K15FV

D 3

10K

2 5% 1/16W MF-LF 402

SOD-VESM-HF

1

C9009 0.001UF


8C5

C9011 0.1UF

3

10% 2 16V X5R 402

1

0.0033UF 1 G 18B6

S 2

R9008 100K

5% 1/16W MF-LF 2 402

18A3 7C7

2

18A3 7C7

10% 50V CERM 402

LVDS_IG_PANEL_PWR

1

R9014

1

1K 5%

1/16W MF-LF 2402

7C7

1

R9009 100K 5% 1/16W MF-LF

2 402

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

P

A

CRITICAL

J9000

20474-030E-11 F-RT-SM 31

1

32

0.001UF 10% 50V X7R

2

2

1

402

7C7 7C3

2

PP3V3_LCDVDD_SW_F

3

69C6

4

BKL_SYNC

5

PP3V3_S0_LCD_F

C

6

MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V

7


18B3 7C7 73B3 18B3 7C7 73B3

18B3 7C7 73B3 73B3 18B3 7C7

LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P

8 9 10


11 12 13

73B3 18B3 7C7 73B3 18B3 7C7

14


15 16

CRITICAL

L9080 90-OHM-200MA AMC2012-SM

LVDS_IG_A_CLK_F_N 7C7 LVDS_IG_A_CLK_F_P

73B3 7C7

17

73B3

18

LVDS I/F

SYM_VER-1

73B3 18B3

73B3 18B3

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

4

3

69C1 7B7 69B1 7B7 69B1 7B7 69B1 7B7

e r

B

C9010

1

(LVDS DDC POWER)

m il

C9013

2

0402-LF

=PP3V3_S0_LCD

10UF

LCDVDD_PWREN_L_R 1

1

C9012

20% 2 6.3V X5R 603

L9008

LVDS CONNECTOR:518S0650

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3VMIN_LINE_WIDTH=0.30 MM

CRITICAL

120-OHM-0.3A-EMI

VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM

1

10% 50V 2 CERM 402

2

0402-LF

PP3V3_LCDVDD_SW

6 5 2 1

G

5% 1/16W MF-LF 2 402

D

100K

S

R9002

C

1

FDC606P_G SOT-6

1

402

FERR-120-OHM-1.5A

CRITICAL

CONNECTOR

69B1 7B7 69B1 7B7

19

1

20

NC 2

69C1 69B3 7C7 7C3

21

PPVOUT_S0_LCDBKLT

22 23

NC

LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6

LED BKLT I/F

24 25 26 27 28 29 30

NC

B

33 34

LVDS CONNECTOR SYNC_MASTER=NMARTIN SYNC_DATE=04/04/2008 NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 90

1

109

A

8

6

7

2

3

4

5

18B6 18B6 18B6 18B6 18B6 18B6 18B6 18B6 18B6

D

18A3 18A3

=MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_TXD_P =MCP_HDMI_TXD_N =MCP_HDMI_HPD =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA

DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_ML_P DP_ML_N DP_HPD

1

BI

33

0.1UF 1

2

5% 1/16W MF-LF 402

Display Port Interoperability spec says that sources or sinks which do both DP and DVI must depend on the external adapter for pull ups on DDC lines (since DP AUX CH has 100K pull up/down on the MLB)..

DP_IG_DDC_CLK 67D1

BI

2

73B3

1

33

5% 1/16W MF-LF 402

2

C9301 0.1UF 1

2

73B3

DP_AUX_CH_SW_P

10% 16V X5R 402

C

3

Q9300

D

SSM6N15FEAPE

Q9300

4

S

SOT563

G 5

2

DP_IG_AUX_CH_P 73B3 18B6

BI

73B3 18B6

BI

=PP5V_S0_DP_AUX_MUX 8D5

1

R9302 100K

5% 1/16W MF-LF 2 402

R9306 1K

5% 1/16W MF-LF 402 2

Q9301

3

D

SSM3K15FV SOD-VESM-HF

2

DP_CA_DET IN

A

68C1 73B3

MAKE_BASE=TRUE 68C1 73C3

MAKE_BASE=TRUE 68C1 73B3

MAKE_BASE=TRUE 68A8

D

67C8

MAKE_BASE=TRUE 67C8

MAKE_BASE=TRUE

S 1

68C8 73B3

C

e r DDC_CA_DET_LS5V_L

B

68B8

G

68C1 73C3

MAKE_BASE=TRUE

m il

DP_IG_AUX_CH_N

1

D 6

SSM6N15FEAPE

SOT563

68B1 73B3

MAKE_BASE=TRUE

y r

68B8 73B3

DP_AUX_CH_C_P

BI

R9301

68C1 73C3

MAKE_BASE=TRUE

a n i

DP_AUX_CH_SW_N

10% 16V X5R 402

68C8 73B3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

C9300

R9300

DP_IG_DDC_DATA 67D1

68C8 73C3

MAKE_BASE=TRUE

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_AUX_CH_C_N BI

1

P

S

G 1

B

DP_IG_CA_DET

OUT

18B6

DISPLAYPORT SUPPORT SYNC_MASTER=AMASON



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 93

1

109

A

8

6

7

2

3

4

5

1

Port Power Switch DP_ESD CRITICAL

CRITICAL

L9400

64D5 41A5 39C5 34B7 21C3 7C3

5 IN

=PP3V3_S5_DP_PORT_PWR

IN

PP3V3_S0_DPILIM

OC* 3

1


TP_DPPWR_OC_L

1

1

10UF 20% 6.3V X5R 603

0.1UF 2

2

C9400

5 IO

1

20% 6.3V X5R 603

10% 16V CERM 402

5% 1/16W MF-LF 402

2

R9401

CRITICAL

2

5%

R9413

0

F-RT-THSM 1

NO STUFF 1

1/16W MF-LF 402

1M

1/16W MF-LF 402

FL9403 12-OHM-100MA IN

DP_ML_P

C9414

73B3 67D1

IN

DP_ML_N

C9415

73B3 67C4

BI

DP_AUX_CH_C_P

BI

DP_AUX_CH_C_N

73C3 67D1

4 1

2 73C3 DP_ML_C_P 10% 16V X5R 402

1

2 73B3 DP_ML_C_N 10% 16V X5R 402

0.1uF 0.1uF

R9425

2

5%

TCM1210-4SM SYM_VER-2

2

5% 1/16W MF-LF 402

BOT ROW

TOP ROW

TH PINS

SM PINS

2

DP_HPD DP_C_A_DET HDMI_CEC GND ML_LANE3P

4 6

1 8 73B3

3

2

73B3

DP_ML_CONN_P DP_ML_CONN_N

10 12

ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR

14

20

DP_ESD CRITICAL

=PP3V3_S0_DPCONN

R9443 1 5% 1/16W MF-LF 402 67A7

OUT

D9411

R9442 1

100K

5% 1/16W MF-LF 402

2

DP_CA_DET

RCLAMP0524P

R9421 1

100K

SLP2510P8

100K 5% 1/16W MF-LF 402

2

2 IO

2

GND

D

Q9440 SOT-363

S

G

2

DP_CA_DET_L_Q

3

3

1

D

Q9440

B

2N7002DW-X-G SOT-363

S

G

DP_CA_DET_Q

5

4

R9422

R9445 1

67D1

OUT

10K 5% 1/16W MF-LF 402

2

DP_HPD 6

R9446 1 100K 5% 1/16W MF-LF 402

2

P

R9444 1

10K 5% 1/16W MF-LF 402

5% 1/16W MF-LF 402

1

MCP79 requires pull Q9441 down HPD input with 2N7002DW-X-G SOT-363 100K if DP_HPD is used.

D

S

G

2

DP_HPD_L_Q

3 5

0

1

9 73B3 11 13 15 17 19

2

DP_ESD CRITICAL

D9400

5%

1/16W MF-LF 402

5%

1/16W MF-LF 402

NO STUFF

0

1

2

10

NO STUFF

0


12-OHM-100MA TCM1210-4SM SYM_VER-2

2

73B3

DP_ML_CONN_N

5%

1/16W MF-LF 402

5%

1/16W MF-LF 402

NO STUFF 1

2

FL9400

1

12-OHM-100MA TCM1210-4SM SYM_VER-2

4

73C3

DP_ML_C_P

TCM1210-4SM SYM_VER-2

2

Q9441 2N7002DW-X-G SOT-363

2

3

73B3

DP_ML_C_N

G

5

1

2

DP_ML_P

10%

16V

C9411

1

2

DP_ML_N

10%

16V

1

2 10%

DP_ML_P

1

2 10%

DP_ML_N

1

2

DP_ML_P

10%

16V

1

2

DP_ML_N

10%

16V

0.1uF 73C3

DP_ML_C_P

C9412

73B3

DP_ML_C_N

C9413

73C3

DP_ML_C_P

C9416

73B3

DP_ML_C_N

C9417

0.1uF 0.1uF

4

0.1uF 3

0.1uF

16V

16V

X5R

X5R

X5R

X5R

X5R

X5R

402

402

402

402

402

402

IN

67D1 73C3

IN

67D1 73B3

IN

67D1 73C3

IN

67D1 73B3

IN

67D1 73C3

IN

67D1 73B3

NO STUFF

R9402

0

R9432

0

1

2

5%

1/16W MF-LF 402

5%

1/16W MF-LF 402

NO STUFF 1

2

DP_ESD CRITICAL

D9411 RCLAMP0524P SLP2510P8

RCLAMP0504F SC70-6-1

5 IO

IO NC

6

1

2

5

6 NC

B

4 7

3

4

3

DisplayPort Connector

D

S

C

C9410 0.1uF

FL9402 12-OHM-100MA

1

DP_ML_CONN_P

2

4

3

73B3

1

0

FL9401

1

7

R9430

NO STUFF

1

3

1

A

2

2

73B3

1

514-0610

10

DP to DVI/HDMI Cable Adapter (CA) has 100k pull-up to DP_PWR.

1M

Q9440 must have Drain to Gate leakage of 5MOhm

=PP3V3_S0_DPCONN

3

1

e r

2N7002DW-X-G

68B8 8B5

IO NC

9 NC

6

GND ML_LANE0P ML_LANE0N GND ML_LANE1P ML_LANE1N73B3 GND ML_LANE2P ML_LANE2N RETURN

SHIELD PINS 22

68A8 8B5

3


73B3

m il 16 18

73B3 67D4

R9431

J9400 DSPLYPRT-M97-2

NO STUFF

21

C

y r

IO NC

R9400

HDMI_CEC

1

9 NC

a n i

1

100K

R9403

2 IO

C9486

20% 2 6.3V X5R-CERM 603

2

R9420

0

4 7

22UF

10UF

20% 10V CERM 402

IO NC

6 NC

CRITICAL

NO STUFF C9485 1

C9481

SLP2510P8

PP3V3_S0_DPPWR MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

0.01UF 2

1

2 0603

GND 2

C9480

SLP2510P8

FERR-120-OHM-3A

TPS2051B SOT23 OUT 1

4 EN

PM_SLP_S3_L

D9410 RCLAMP0524P

GND

8A3

D

D9410 RCLAMP0524P

GND

U9480

GND

D

DP_ESD CRITICAL

SYNC_MASTER=AMASON

DP_HPD_Q



4

R9423

1

100K 5% 1/16W MF-LF 402

DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

2


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 94

1

109

A

8

6

7

2

3

4

5

1

*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER. *BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

CRITICAL PLACEMENT_NOTE=Place near Q9701

L9701

D9701

22UH-2.5A

PPBUS_S0_LCDBKLT_PWR

2

VOLTAGE=12.6V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.4 mm

D

PPVIN_S0_LCDBKLT_BUF

1

1

VOLTAGE=12.6V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM

R9730 0.1 1% 1/6W MF 402-HF

R9701 1% 1/16W MF-LF 402

1

C9701 10UF

2

PPVOUT_S0_LCDBKLT_SW

1

VOLTAGE=30V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm SWITCH_NODE=TRUE

1

1

1

GND_BKL_PWRGND

69D7 69C3 69B4

2


PLACEMENT_NOTE=Place near C9701

1

Q9701 S 4

C9702

C9710 4.7UF

10% 50V X7R-CERM 1206

2

10% 50V X7R-CERM 1206



10% 25V X5R 402

1

C9709

2

SSOT6


CRITICAL

4.7UF

FDC5612

G

3

0.1UF

2

y r

D

BOOST_FET_CNTL

PLACEMENT_NOTE=Place near L9701

GND_BKL_PWRGND

D

CRITICAL

5 6

CRITICAL

BKL_VIN

XW9701 SM 69D6 69C3 69B4

2

PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW

10% 25V X5R 805

PLACEMENT_NOTE=Place near J9000

2

DFLS1100

PLACEMENT_NOTE=Place near Q9701

100 CRITICAL


POWERDI-123 2

IHLP2525CZ-SM

2

IN

1

70C3 69C7

BOOST_SINK

69D7 69D6 69B4

GND_BKL_PWRGND

PLACEMENT_NOTE=Place near C9709 and Q9701

a n i

BKLT_EN 187K

2

BKLT_PLL

1% 1/16W MF-LF 402

66C2

BKL_SYNC

IN

2

BKL_VSYNC

1

2

2

C9713 0.1UF

100K

10% 25V X5R 402

1% 1/16W MF-LF 402

2

R9706

XW9702 SM 1

2

2 1

PLACEMENT_NOTE=Place near C9709 and Q9701

VIN

10K 1

1% 1/16W MF-LF 402

10% 10V X5R 402-1

0.4

1% 1/6W MF 402

*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

5% 1/16W MF-LF 402

R9705

2

1UF

3.01K 1

1

1

2

C

C9703

1

R9715

0.4

1% 1/6W MF 402


R9734 0

R9707

R9702

100

1% 1/16W MF-LF 402

GND_BKL_PWRGND_X

3

1

BKL_VREF_4V9

1

U9701

5% 1/16W MF-LF 402

4 VREF 5 ENA 17 VSYNC

C9712 47PF

DRV 1

QFN

APP001A

69D7 70C3

69A8 7C3 69C4 69B6

1

R9731 PPBUS_S0_LCDBKLT_PWR

R9704

2

7C3 69A8 69B6 69C8

1

2

BKL_VREF_4V9

2

ISWSEN 2 ISEN1 10

PPVOUT_S0_LCDBKLT

5% 50V CERM 402

BKL_ISET

R9717 10.2

1

2

2

2.0M

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

5% 1/16W MF-LF 402

1

2

R9703

1K 1

C9706 0.0022UF

NOSTUFF

2

10% 50V CERM 402

5% 1/16W MF-LF 402

1

2

BKL_LRT

10% 10V X5R 402

R9713

Q9702

BKLT_PLL_NOT

NTUD3127CXXG SOT-963

1

5

2

N-CHN

Q9702 NTUD3127CXXG

R9711

6

30.1K 1% 1/16W MF-LF 402

1

A

2

1% 1/16W MF-LF 402

D

SOT-963

LVDS_IG_BKL_PWM

R9710 10K

BKL_PWR_EN_L CRITICAL

P

BKL_VREF_IN_4V9

2

P-CHN

100K 1% 1/16W MF-LF 402

3

G

R9700

D

4

S

BKL_VREF_4V9

G S

1

69D7 69D6 69C3

C9707 2.2UF

2

20% 6.3V CERM 402-LF

1


OUT

7B7 66B3

10.2

LED_RETURN_3

2


0.1%

OUT

7B7 66B3

OUT

7B7 66B3

OUT

7B7 66B3

OUT

7B7 66B3

1/16W TF 402

R9720

THRM_PAD

1

10.2


LED_RETURN_4

2


0.1% 1/16W TF 402

R9721 1

GND_BKL_PWRGND

10.2


LED_RETURN_5

2


0.1%

B

1/16W TF 402

R9722 10.2 1

R9727

LED_RETURN_6

2



0.1% 1/16W TF 402

15.0K

BKLT_PLL BKL_LRT_RC

7B7 66B3

R9719 1


R9714 5% 1/16W MF-LF 402

LED_RETURN_2

2 0.1%

BKL_ISEN6

BKLT_PLL

10K

OUT

1/16W TF 402

PLACEMENT_NOTE=Away from Q9701

BKLT_PLL 1

10.2

BKL_ISEN5

1% 1/16W MF-LF 402

PPVOUT_S0_LCDBKLT


7C3 7C7 66B2 69C1

C9708 0.1UF

2

10% 25V X5R 402

2

CRITICAL

VSEN 9


R9718 1


R9723 1.2M

1

1

5% 1/16W MF-LF 402


IN

18 LRT

BKL_ISEN4

1% 1/10W MF-LF 603

BKL_VSEN

LCD BACKLIGHT DRIVER 2

2

BKL_VREF_4V9

0

70A7 18B6

ISEN6 16

BKL_ISEN3

R9724

SYNC_MASTER=YITE


71.5K 1

69C4 69A8 7C3 69C8

B

69C8 69C4 69B6 7C3

ISEN5 15

19 LPF

13

20% 10V CERM 402

1

0.1UF

2

e r

C9705

ISEN4 14

20 DIM

GNDA

NOSTUFF

2

BKL_SSTCMP_RC

2

C9714 1UF

NOSTUFF

1

7 SSTCMP

BKL_LPF

0 1

6 RT

BKL_SSTCMP BKL_DIM

1

R9733

1

1

2

BKLT_PWM_RC

R9709

BKL_RT

LED_RETURN_1

2

0.1% 1/16W TF 402

BKL_ISEN2

21


R9708

ISEN2 11 CRITICAL ISEN3 12

m il


100K

8 ISET


1% 1/16W MF-LF 402


DRAWING NUMBER

D APPLE INC. *R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT

7

6

5

4

3

2

REV.

051-7537

SCALE

SHT NONE

8

C

NOSTUFF

BKL_ISEN1



7C3 7C7 66B2 69B3

OUT

VOLTAGE=30V MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm

A

OF 97

1

109

A

8

6

7

2

3

4

5

1

Q9806 FDC638APZ_SBMS001

PPBUS S0 LCDBkLT FET


0402-HF

PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

1

R9808

1

FDC638APZ

CHANNEL

P-TYPE

LOADING

0.1UF

1%

10% 16V X5R 402

1/16W

2

MF-LF

RDS(ON)

D

43 mOhm @4.5V

C9802

301K

2

MOSFET

1

IN

2

402

y r

0.4 A (EDP)

3

D

1

=PPBUS_S0_LCDBKLT

4

2AMP-32V 8C1

6

F9800

2 5

SSOT6-HF

PPBUS_S0_LCDBKLT_EN_DIV

1

R9809 147K 1% 1/16W MF-LF

2

402

PPBUS_S0_LCDBKLT_EN_L

Q9807

D

a n i

3

SSM6N15FEAPE SOT563

5 70B7 18B6

LVDS_IG_BKL_ON

IN

G

S

PPBUS_S0_LCDBKLT_PWR

4


BKLT_EN_L

Q9807

D

6

S

1

SSM6N15FEAPE SOT563

C

2 26C1

BKLT_PLT_RST_L

IN

1

R9840 1K

2

5% 1/16W MF-LF 402

1

R9841 1K 5% 1/16W MF-LF

2 402

A

P

18B6 70C8 18B6 69A8

69C7 69D7

C

m il

e r

B

LVDS_IG_BKL_ON LVDS_IG_BKL_PWM

G

OUT

B

LCD Backlight Support SYNC_MASTER=YITE



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

.

REV.

051-7537

A

OF 98

1

109

A

8

6

7

FSB (Front-Side Bus) Constraints

2

3

4

5

1

CPU / FSB Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

FSB_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

NET_TYPE ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

FSB_DATA_GROUP0

FSB_50S

FSB_DATA

FSB_DATA_GROUP0

FSB_50S

FSB_DATA

FSB_DSTB0

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB0

FSB_DSTB_50S

FSB_DSTB

FSB_DATA_GROUP1

FSB_50S

FSB_DATA

FSB_DATA_GROUP1

FSB_50S

FSB_DATA

FSB_DSTB1

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB1

FSB_DSTB_50S

FSB_DSTB

FSB_DATA_GROUP2

FSB_50S

FSB_DATA

FSB_DATA_GROUP2

FSB_50S

FSB_DATA

FSB_DSTB2

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB2

FSB_DSTB_50S

FSB_DSTB

FSB_DATA_GROUP3

FSB_50S

FSB_DATA

FSB_DATA_GROUP3

FSB_50S

FSB_DATA

FSB_DSTB3

FSB_DSTB_50S

FSB_DSTB

FSB_DSTB3

FSB_DSTB_50S

FSB_DSTB

FSB_ADDR_GROUP0

FSB_50S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_50S

FSB_ADDR

FSB_ADSTB0

FSB_50S

FSB_ADSTB

FSB_ADDR_GROUP1

FSB_50S

FSB_ADDR

FSB_ADSTB1

FSB_50S

FSB_ADSTB

FSB_1X

FSB_50S

FSB_1X

FSB_BREQ0_L

FSB_50S

FSB_1X

FSB_BREQ1_L

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X


*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LINE-TO-LINE SPACING

WEIGHT

FSB_DATA

LAYER *

=2x_DIELECTRIC

?

FSB_DSTB

*

=3x_DIELECTRIC

?


SPACING_RULE_SET


WEIGHT

FSB_DATA

TOP,BOTTOM

LAYER

=4x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM



D



FSB_ADDR

*

=STANDARD


?

FSB_ADDR

TOP,BOTTOM

=3x_DIELECTRIC

?


FSB_ADSTB

*

=2x_DIELECTRIC


?

FSB_ADSTB

TOP,BOTTOM

=4x_DIELECTRIC

?


FSB_1X

*

=STANDARD

FSB 4X Signal Groups

FSB_DSTB_50S


?

FSB_1X

TOP,BOTTOM

=3x_DIELECTRIC

?

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

FSB 2X Signals

FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

FSB 1X Signals

Design Guide recommends each strobe/signal group is routed on the same layer. Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

C

PHYSICAL_RULE_SET

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM

CPU_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_CPURST_L

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

FSB_1X

FSB_50S

FSB_1X

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_BSEL

CPU_50S

CPU_AGTL

CPU_FERR_L

CPU_50S

CPU_8MIL

CPU_ASYNC

CPU_50S

CPU_AGTL

=STANDARD TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

*

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

7 MIL

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER


WEIGHT

=STANDARD

?


SPACING_RULE_SET

LAYER


WEIGHT

=2x_DIELECTRIC

?


CPU_AGTL

*


CPU_AGTL

TOP,BOTTOM

m il


CPU_8MIL

*

8 MIL

? TABLE_SPACING_RULE_ITEM

CPU_COMP

*

25 MIL


CPU_GTLREF

*

SR DG recommends at least 25 mils, >50 mils preferred

?

25 MIL


CPU_ITP

*

=2:1_SPACING

?

CPU_VCCSENSE

*

25 MIL

?


Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

e r

MCP FSB COMP Signal Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MCP_50S

*

=50_OHM_SE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD


B


SPACING_RULE_SET

LAYER


WEIGHT TABLE_SPACING_RULE_ITEM

MCP_FSB_COMP

*

8 MIL

?

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB Clock Constraints


PHYSICAL_RULE_SET

LAYER

CLK_FSB_100D

*


MINIMUM LINE WIDTH

=100_OHM_DIFF

MINIMUM NECK WIDTH

=100_OHM_DIFF

=100_OHM_DIFF


SPACING_RULE_SET

LAYER


WEIGHT

SPACING_RULE_SET


CLK_FSB

*

=3x_DIELECTRIC

?

CLK_FSB


A

P

MAXIMUM NECK LENGTH =100_OHM_DIFF

LAYER

TOP,BOTTOM


DIFFPAIR NECK GAP


=100_OHM_DIFF

LINE-TO-LINE SPACING =4x_DIELECTRIC

CPU_INIT_L

CPU_50S

CPU_AGTL

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_50S

CPU_AGTL

PM_THRMTRIP_L

CPU_50S

CPU_8MIL

FSB_CPUSLP_L

CPU_50S

CPU_AGTL

CPU_FROM_SB

CPU_50S

CPU_AGTL

CPU_DPRSTP_L

CPU_50S

CPU_AGTL

CPU_ASYNC

CPU_50S

CPU_AGTL

MCP_CPU_COMP

MCP_50S

MCP_FSB_COMP

MCP_CPU_COMP

MCP_50S

MCP_FSB_COMP

MCP_CPU_COMP

MCP_50S

MCP_FSB_COMP

MCP_CPU_COMP

MCP_50S

MCP_FSB_COMP

FSB_CLK_CPU

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

CLK_FSB_100D

CLK_FSB

CPU_IERR_L

CPU_50S

PM_DPRSLPVR

CPU_50S

CPU_AGTL

(See above)

CPU_50S

CPU_AGTL

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_COMP

CPU_50S

CPU_COMP

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_COMP

CPU_50S

CPU_COMP

CPU_COMP

CPU_27P4S

CPU_COMP

XDP_TDI

CPU_50S

CPU_ITP

XDP_TDO

CPU_50S

CPU_ITP

XDP_TMS

CPU_50S

CPU_ITP

XDP_TCK

CPU_50S

CPU_ITP

XDP_TRST_L

CPU_50S

CPU_ITP

XDP_BPM_L

CPU_50S

CPU_ITP

XDP_BPM_L5

CPU_50S

CPU_ITP

(FSB_CPURST_L)

CPU_50S

CPU_ITP

CPU_50S

CPU_8MIL

CPU_50S

CPU_8MIL

CPU_27P4S

CPU_VCCSENSE



FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N FSB_A_L FSB_REQ_L FSB_ADSTB_L FSB_A_L FSB_ADSTB_L FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_TRDY_L

CPU_A20M_L CPU_BSEL CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L

=100_OHM_DIFF

WEIGHT

FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N

10C4 14D3 10C4 14D6 10C4 14D6 10C4 14D6

10B4 10C4 14C3 14D3 10B4 14D6 10B4 14D6

D

10B4 14D6

10C2 14B3 14C3

y r

10C2 14D6 10C2 14D6 10C2 14D6

10B2 10C2 14B3 10B2 14D6 10B2 14D6 10B2 14D6

10D8 14C6 14D6 10D8 14B6

10D8 14B6

a n i

FSB_1X FSB_1X



FSB_D_L FSB_DINV_L FSB_DSTB_L_P FSB_DSTB_L_N

10C8 14B6 14C6 10C8 14B6

10D6 14B6

9B2 10D6 14B6 14B6

10D6 14B6 10D6 14B3 10D6 14B6 10D6 14B3 10D6 14B6 10C6 14B6 10C6 14B6

C

10D6 14B6

9B2 10D6 13B2 14A3 10D6 14A6 10D6 14B6

10C8 14A3

9C2 10A4 10B4 10C8 14B7 10C8 14A3 10D6 14A3 9B2 10B8 14A3 9B2 10B8 14A3 10C5 14B6 40D4 60C8 10B2 13C7 14A3 10B8 14A3 10B8 14A3 10C6 14B7 40C4 10A2 14A3 10B2 14A3 9B2 10B2 14A3 60C7 10B2 14A3 14A6 14A6 14A6 14A6

10B6 14B3 10B6 14B3

B

13C3 14A3 13B3 14A3 14A4 14A4

10D6

PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP

21C7 60D8 60C7

10B4 27B1 10B3 10B3 10B3 10B3

?

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

(CPU_VCCSENSE) (CPU_VCCSENSE)

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VID IMVP6_VID CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N

6C6 10B6 10C6 13B3 6C4 10B6 10C6 6C6 6C7 10B6 10C6 13B3 6C6 6C7 10A6 10C6 13B6 6C6 6C7 10A6 10C6 13B3 10C6 13C6 10C5 13C6 13B4

11B6 60C7

CPU/FSB Constraints 11A5 60A5

SYNC_MASTER=T18_MLB


11A5 60A5


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 100

1

109

A

8

6

7

Memory Bus Constraints

2

3

4

5

1

Memory Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

MEM_40S

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD


PHYSICAL

SPACING


MEM_A_CLK

MEM_70D_VDD

MEM_CLK

MEM_A_CLK

MEM_70D_VDD

MEM_CLK

MEM_A_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_A_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_A_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_DQ_BYTE0


MEM_40S_VDD

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD


15B5 28C5 28C7 15B5 28C5 28C7


MEM_70D

*

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

MEM_70D_VDD

*

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF



SPACING_RULE_SET

D

LAYER


WEIGHT

=4:1_SPACING

?


MEM_CLK2MEM

*


MEM_CTRL2CTRL

*

=2:1_SPACING

?

MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

15A5 28D5 28D7 15B5 28C5 28C7 15A5 28C5

15B5 15C5 28C5 28C7 15C5 28C5 28C7

15C5 28C7

y r

15C5 28C7


MEM_CTRL2MEM

*

=2.5:1_SPACING

?

MEM_CMD2CMD

*

=1.5:1_SPACING

?

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_40S

MEM_DATA

MEM_A_DQS0

MEM_70D

MEM_DQS

MEM_A_DQS0

MEM_70D

MEM_DQS

MEM_A_DQS1

MEM_70D

MEM_DQS

MEM_A_DQS1

MEM_70D

MEM_DQS

MEM_A_DQS2

MEM_70D

MEM_DQS

MEM_A_DQS2

MEM_70D

MEM_DQS

MEM_A_DQS3

MEM_70D

MEM_DQS

MEM_A_DQS3

MEM_70D

MEM_DQS

MEM_A_DQS4

MEM_70D

MEM_DQS

MEM_A_DQS4

MEM_70D

MEM_DQS

MEM_A_DQS5

MEM_70D

MEM_DQS

MEM_A_DQS5

MEM_70D

MEM_DQS

MEM_A_DQS6

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS



MEM_CMD2MEM

*

=3:1_SPACING


MEM_DATA2DATA

*

=1.5:1_SPACING


MEM_DATA2MEM

*

=3:1_SPACING


MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

15B7 28C2 28C4 28D2 28D4 15B7 28C2 28C4

15B7 15C7 28B2 28B4 28C2 28C4 15C7 28C2 28C4 15C7 28B5 28B7 15C7 28B5 28B7 15D7 28B5 28B7 15D7 28A5 28A7


MEM_2OTHER

*

25 MIL

?

Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

MEM_CLK

*

MEM_CLK2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CLK

*

MEM_CMD2MEM


MEM_CLK

MEM_CTRL

*

MEM_CLK2MEM

MEM_CLK

MEM_CMD

*

MEM_CLK2MEM


MEM_CMD

MEM_CTRL

*

MEM_CMD2MEM

MEM_CMD

MEM_CMD

*

MEM_CMD2CMD

MEM_CMD

MEM_DATA

*

MEM_CMD2MEM

MEM_CMD

MEM_DQS

*

MEM_CMD2MEM




MEM_CLK

MEM_DATA

*

MEM_CLK2MEM

MEM_CLK

MEM_DQS

*

MEM_CLK2MEM




TABLE_SPACING_ASSIGNMENT_HEAD

C

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CTRL

MEM_CLK

*

MEM_CTRL2MEM


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DATA

MEM_CLK

*

MEM_DATA2MEM




MEM_CTRL

MEM_CTRL

*

MEM_CTRL2CTRL

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM


MEM_DATA

MEM_CTRL

*

MEM_DATA2MEM

MEM_DATA

MEM_CMD

*

MEM_DATA2MEM




MEM_CTRL

MEM_DATA

*

MEM_CTRL2MEM


MEM_DATA

MEM_DATA

*

MEM_DATA2DATA


MEM_CTRL

MEM_DQS

*

MEM_CTRL2MEM


MEM_DATA

MEM_DQS

*

MEM_DATA2MEM


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

MEM_DQS

MEM_CTRL

*

MEM_DQS2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

*

*

MEM_2OTHER

MEM_CTRL

*

*

MEM_2OTHER




MEM_CMD

*

MEM_DQS2MEM


MEM_CMD

*

*

MEM_2OTHER


MEM_DATA

MEM_DQS

*

MEM_DQS2MEM


MEM_DATA

*

*

MEM_2OTHER


MEM_DQS

MEM_DQS

*

MEM_DQS2MEM

m il



MEM_DQS

MEM_A_DQS6



MEM_DQS

*

*

MEM_2OTHER

Need to support MEM_*-style wildcards!

DDR2:

B

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

e r

DDR3: DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MCP MEM COMP Signal Constraints PHYSICAL_RULE_SET

LAYER

MCP_MEM_COMP

*


MINIMUM LINE WIDTH

Y

MINIMUM NECK WIDTH

7 MIL

7 MIL


SPACING_RULE_SET

LAYER



MCP_MEM_COMP

*

8 MIL

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

A

P

MAXIMUM NECK LENGTH =STANDARD

DIFFPAIR PRIMARY GAP =STANDARD

MEM_A_DQS7

MEM_70D

MEM_DQS

MEM_A_DQS7

MEM_70D

MEM_DQS

MEM_B_CLK

MEM_70D_VDD

MEM_CLK

MEM_B_CLK

MEM_70D_VDD

MEM_CLK

MEM_B_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_B_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_CMD

MEM_40S_VDD

MEM_CMD

MEM_B_DQ_BYTE0

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_40S

MEM_DATA

MEM_B_DQS0

MEM_70D

MEM_DQS

MEM_B_DQS0

MEM_70D

MEM_DQS

MEM_B_DQS1

MEM_70D

MEM_DQS

MEM_B_DQS1

MEM_70D

MEM_DQS

MEM_B_DQS2

MEM_70D

MEM_DQS

MEM_B_DQS2

MEM_70D

MEM_DQS

MEM_B_DQS3

MEM_70D

MEM_DQS

MEM_B_DQS3

MEM_70D

MEM_DQS

MEM_B_DQS4

MEM_70D

MEM_DQS

MEM_B_DQS4

MEM_70D

MEM_DQS

MEM_B_DQS5

MEM_70D

MEM_DQS

MEM_B_DQS5

MEM_70D

MEM_DQS

MEM_B_DQS6

MEM_70D

MEM_DQS


DIFFPAIR NECK GAP


15A7 28C4

a n i



MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM

D

15C5 28C5

=STANDARD

MEM_B_DQS6

MEM_70D

MEM_DQS

MEM_B_DQS7

MEM_70D

MEM_DQS

MEM_B_DQS7

MEM_70D

MEM_DQS

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

15A7 28C2 15A7 28B4 15A7 28C2 15A7 28B5 15B7 28B7 15B7 28B5 15B7 28A7

MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N

MEM_B_CLK_P MEM_B_CLK_N MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM

15D5 28C2 15D5 28C2 15D5 28C4 15D5 28C4 15D5 28B2 15D5 28B2

C

15D5 28C4 15D5 28C4 15D5 28B7 15D5 28B7 15D5 28B5 15D5 28B5 15D5 28B7 15D5 28B7 15D5 28A5 15D5 28A5

15B1 29C5 29C7 15B1 29C5 29C7

15A1 29D5 29D7 15B1 29C5 29C7 15A1 29C5

15B1 15C1 29C5 29C7 15C1 29C5 29C7 15C1 29C5 15C1 29C7 15C1 29C7

15B3 29C2 29C4 29D2 29D4 15B3 29C2 29C4 15B3 15C3 29C2 29C4 15C3 29B2 29B4 29C2 29C4

B

15C3 29B5 29B7 15C3 29B5 29B7 15D3 29B5 29B7 15D3 29A5 29A7

15A3 29C4 15A3 29C2 15A3 29C2 15A3 29B4 15A3 29B5 15B3 29B7 15B3 29B5 15B3 29A7

MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

15D1 29C2 15D1 29C2 15D1 29C4 15D1 29C4 15D1 29C4 15D1 29C4 15D1 29B2 15D1 29B2 15D1 29B7 15D1 29B7 15D1 29B5

Memory Constraints

15D1 29B5 15D1 29B7

SYNC_MASTER=T18_MLB


15D1 29B7


15D1 29A5 15D1 29A5


16C6


16C6


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 101

1

109

A

8

6

7

2

3

4

5

1

NET_TYPE

PCI-Express

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE



CLK_PCIE_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

PCIE_MINI_R2D

=100_OHM_DIFF PCIE_MINI_D2R


SPACING_RULE_SET

LAYER


SPACING_RULE_SET

LAYER


WEIGHT


*

=3X_DIELECTRIC

?

CLK_PCIE

*

20 MIL

?

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE


WEIGHT

PCIE

PCIE_90D

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

D


*

8 MIL

PCIE_FC_R2D

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

PCIE_FC_D2R

MCP_PE1_REFCLK

MCP_PE4_REFCLK

MCP_PEX_COMP

Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



DP_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

MCP_DV_COMP

*

Y

20 MIL

20 MIL

=STANDARD

=STANDARD

=STANDARD

SPACING_RULE_SET

LAYER





SPACING_RULE_SET

LAYER


*

=3x_DIELECTRIC


?

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?


LVDS

*

=3x_DIELECTRIC


?

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


SATA_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

SATA_100D_HDD

*

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD

=100_OHM_DIFF_HDD

SPACING_RULE_SET

LAYER

DIFFPAIR NECK GAP

e r TABLE_PHYSICAL_RULE_ITEM



B

=4x_DIELECTRIC

?


SPACING_RULE_SET

LAYER


WEIGHT

=3x_DIELECTRIC

?


SATA

*


SATA

TOP,BOTTOM


SATA_TERMP

*

8 MIL

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

P

A

DISPLAYPORT

DP_100D

DISPLAYPORT

TMDS_IG_TXD

DP_100D

DISPLAYPORT

TMDS_IG_TXD

DP_100D

DISPLAYPORT

DP_ML

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_AUX_CH

SATA Interface Constraints

WEIGHT

DP_100D

TMDS_IG_TXC

DP_ML

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.


TMDS_IG_TXC

m il



DISPLAYPORT

7D5 31C7 17B3 31C5 17B3 31C5 7D5 17B6 31C7 7D5 17B6 31C7

32C5 32C5

9B5 32C6

MCP_DV_COMP

MCP_HDMI_VPROBE

MCP_DV_COMP

LVDS_IG_A_CLK

LVDS_100D

LVDS

LVDS_100D

LVDS

LVDS_100D

LVDS

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA

LVDS_100D

LVDS

DP_ML

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

I182

MCP_IFPAB_RSET

SATA_HDD_R2D

SATA_HDD_D2R

SATA_ODD_R2D

SATA_ODD_D2R

DP_ML_P DP_ML_C_P DP_ML_N DP_ML_C_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_AUX_CH_SW_P DP_AUX_CH_SW_N DP_AUX_CH_C_P DP_AUX_CH_C_N

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_N LVDS_IG_A_CLK_F_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N


SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

SATA_TERMP

MCP_SATA_TERMP

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D_HDD

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

9B5 32B5

17C3 31C5 17C3 31C5 7D5 31C8

7D5 31C8

9B5 32C5 9B5 32C5

17A6

67D1 68C1 68C8 68C2 68C7 67D1 68B1 68C1 68C8 68B2 68C2 68C7 18B6 67C7 18B6 67B7 67C6 67C5 67C4 68C8 67D4 68B8

18A6 25C7 18A6 25C7

18B3 66B3 7C7 66B2 18B3 66B3 7C7 66B2

B

7C7 18B3 66C2 7C7 18B3 66C2

68C3 68C4 68C5 68B3 68C3 68C4 68C5

18A3 25C6 18A3 25C6

20D6 36A3 20D6 36A3 7C5 36A7 7C5 36A7 36A5 36A5 20D6 36A3 20D6 36A3 7C5 36A7 7C5 36A7 36A5

MCP Constraints 1

36A5 20D6 36C2

SYNC_MASTER=T18_MLB


20D6 36C2


7B7 36B5 7B7 7C5 36B5


36C4 36C4

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 20D6 36B2

II NOT TO REPRODUCE OR COPY IT 20D6 36B2

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART 7B7 36B5

SIZE

7B7 36B5

DRAWING NUMBER

D

36B4 36B4

APPLE INC. MCP_SATA_TERMP

C

TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P TMDS_IG_TXD_N


MCP_DV_COMP

MCP_IFPAB_VPROBE

9B5 32B5

y r

PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N

MCP_PEX_CLK_COMP

D

9B5 32C6

PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N

MCP_HDMI_RSET MCP_HDMI_VPROBE

MCP_HDMI_RSET

LVDS_IG_A_CLK

I183

PCIE_FC_R2D_P PCIE_FC_R2D_N PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N PCIE_FC_D2R_P PCIE_FC_D2R_N

a n i

MCP_PEX_CLK_COMP

C

7D5 31C7



MCP_PEX_COMP

PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N

SCALE

SHT

20A6

NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 102

1

109

A

8

6

7

2

3

4

5

1

PCI Bus Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

PCI_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


PHYSICAL

SPACING


MCP_DEBUG

PCI_55S

PCI

PCI_AD

PCI_55S

PCI

PCI_AD24

PCI_55S

PCI

PCI_AD

PCI_55S

PCI

PCI_AD

PCI_55S

PCI

PCI_C_BE_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_REQ0_L

PCI_55S

PCI

PCI_GNT0_L

PCI_55S

PCI

PCI_REQ1_L

PCI_55S

PCI

PCI_GNT1_L

PCI_55S

PCI

PCI_INTW_L

PCI_55S

PCI

PCI_INTX_L

PCI_55S

PCI

PCI_INTY_L

PCI_55S

PCI

PCI_INTZ_L

PCI_55S

PCI

MCP_PCI_CLK2

CLK_PCI_55S

CLK_PCI

CLK_PCI_55S

CLK_PCI

LPC_AD

LPC_55S

LPC

LPC_FRAME_L

LPC_55S

LPC

LPC_RESET_L

LPC_55S

LPC


CLK_PCI_55S

*

SPACING_RULE_SET

LAYER

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD




PCI

*

=STANDARD


CLK_PCI

D

*

8 MIL

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



LPC_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD TABLE_PHYSICAL_RULE_ITEM

CLK_LPC_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


SPACING_RULE_SET

LAYER


WEIGHT

6 MIL

?


LPC

*


CLK_LPC

*

8 MIL

USB 2.0 Interface Constraints ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



MCP_USB_RBIAS

*

=STANDARD

8 MIL

8 MIL

=STANDARD

=STANDARD

=STANDARD

USB_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

MCP_LPC_CLK0 TABLE_PHYSICAL_RULE_ITEM


SPACING_RULE_SET

LAYER


WEIGHT

=2x_DIELECTRIC

?


SPACING_RULE_SET

LAYER


WEIGHT

=4x_DIELECTRIC

?


USB

C

*

USB_EXTA

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB


USB

TOP,BOTTOM


SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

SMB_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

SPACING_RULE_SET

LAYER


USB_CAMERA TABLE_SPACING_RULE_HEAD


m il


SMB

*

=2x_DIELECTRIC

?

USB_BT


HD Audio Interface Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH



HDA_55S

*

SPACING_RULE_SET

LAYER

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD



*

=2x_DIELECTRIC

?

USB_EXTB

e r


*

MCP_HDA_COMP

?

8 MIL


B

SIO Signal Constraints


PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP


CLK_SLOW_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD


SPACING_RULE_SET

LAYER



CLK_SLOW

*

8 MIL

?


SPI Interface Constraints

P

=STANDARD

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

SPI_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


LAYER



SPI

*

8 MIL

?


A

PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD LPC_FRAME_L LPC_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N CONN_USB_EXTA_P CONN_USB_EXTA_N

USB_CAMERA_P USB_CAMERA_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N CONN_USB2_BT_P CONN_USB2_BT_N USB_TPAD_P USB_TPAD_N USB_TPAD_R_P USB_TPAD_R_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N CONN_USB_EXTB_P CONN_USB_EXTB_N

y r

19D2 19D7

19D2 19D7

MCP_USB_RBIAS_GND

MCP_USB_RBIAS

SMBUS_MCP_0_CLK

SMB_55S

SMB

SMBUS_MCP_0_DATA

SMB_55S

SMB

SMBUS_MCP_1_CLK

SMB_55S

SMB

SMBUS_MCP_1_DATA

SMB_55S

SMB

HDA_BIT_CLK

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R

MCP_HDA_COMP

MCP_HDA_PULLDN_COMP

CLK_SLOW_55S

CLK_SLOW

CLK_SLOW_55S

CLK_SLOW

PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

HDA_SYNC

HDA_RST_L


HDA_SDIN0

HDA_SDOUT

MCP_HDA_PULLDN_COMP MCP_SUS_CLK

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS0

19C5 19C5

19B3 39C8 41D3 41D5 19C3 39C8 41D5 19B3 26D4

19B3 26C4 26C1 39C8 26B1 41D3

20D3 37A8 20D3 37A8 37C4 37C4

C

37C3 37C3

20D3 31B5 20D3 31B5 7D5 31B7 7D5 31B7 20C3 31B5 20C3 31B5 7C5 31B7 7C5 31B7 20D3 47B8 20D3 47B8

47B7 47B7

20D3 38C7 20D3 38C7 20C3 37A4 20C3 37A4 37A3 37A3

B

MCP_USB_RBIAS


PHYSICAL_RULE_SET

SPACING_RULE_SET

USB_TPAD

USB_IR


HDA

D

a n i


LAYER

13C3 19D7

?


PHYSICAL_RULE_SET

MCP_DEBUG PCI_AD PCI_AD PCI_AD PCI_PAR PCI_C_BE_L PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA

SPI_CLK_R SPI_CLK SPI_ALT_CLK SPI_MOSI_R SPI_MOSI SPI_ALT_MOSI SPI_MISO SPI_MISO_R SPI_ALT_MISO SPI_CS0_R_L SPI_CS0_L

20B4

13B6 21C3 42D8 13B6 21C3 42D8 21C3 42C8 21C3 42C8

21D2 51C7 21A7 21D4 21C2 51C7 21A7 21C4 21A7 21D4 21D2 51B7 21D7 51C7

21D2 51C7 21A7 21D4

21C7

21B3 26B4 26B1 39C5

MCP Constraints 2

21B3 41A5 41C8 41A1 50C5

SYNC_MASTER=T18_MLB

41C5 41D3 21B3 41A5 41C7



41B1 50C4


41C5 41D5 21B3 41A5 41B7


50C4


41B5 41D5


21B3 41B7

SIZE

SPI_CS1_R_L SPI_CS1_R_L_USE_MLB

DRAWING NUMBER

D 41B2

APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 103

1

109

A

8

6

7

2

3

4

5

1

MCP RGMII (Ethernet) Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

MCP_MII_COMP

*

=STANDARD

7.5 MIL

7.5 MIL

=STANDARD

=STANDARD

=STANDARD


PHYSICAL

SPACING


MCP_MII_COMP_VDD MCP_MII_COMP_GND

MCP_MII_COMP

MCP_MII_COMP

MCP_MII_COMP

MCP_MII_COMP

MCP_CLK25M_BUF0

ENET_MII_55S

MCP_BUF0_CLK

ENET_MII_55S

MCP_BUF0_CLK

ENET_MII_55S

ENET_MII


ENET_MII_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD


SPACING_RULE_SET

LAYER


WEIGHT

MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1

18C6 18C6

18C3 34A5 33B6 34A3


MCP_BUF0_CLK

*

=3:1_SPACING

?

ENET_MII

*

12 MIL

?

ENET_INTR_L TABLE_SPACING_RULE_ITEM

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

ENET_MDIO

ENET_MII_55S

ENET_MII

ENET_MDC

ENET_MII_55S

ENET_MII

ENET_PWRDWN_L

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_RXD

ENET_MII_55S

ENET_MII

ENET_RXD_STRAP

ENET_MII_55S

ENET_MII

ENET_RXD

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_TXCLK

ENET_MII_55S

ENET_MII

ENET_TXD0

ENET_MII_55S

ENET_MII

ENET_TXD

ENET_MII_55S

ENET_MII

ENET_TXD

ENET_MII_55S

ENET_MII

ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD ENET_TXD ENET_TX_CTRL

ENET_MII_55S

ENET_MII

ENET_RESET_L

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_P ENET_MDI_N ENET_MDI_TRAN_P ENET_MDI_TRAN_N

ENET_RXCLK TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

ENET_MDI_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF



SPACING_RULE_SET

LAYER


WEIGHT

25 MIL

?


ENET_MDI

*


ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R ENET_RXD ENET_RXD ENET_RX_CTRL ENET_RXCTL_R

18C3 33B6 18C3 33B6

D

33C4

y r

18D6 33C1 33B4 33C4 18D6 33C1

18D6 33B1 33C1 18D6 33B1 33B4

33C6

18D3 33C8 18D3 33C6

18D3 33B6 33C6

a n i

ENET_MDI

C

18C3 33B6

18C3 33B7

33B3 35B7 35C7 33B3 35B7 35C7 35B4 35C4 35C5 35B4 35C4 35C5

C

m il

e r

B

P

A

B

Ethernet Constraints SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 104

1

109

A

8

6

7

2

3

4

5

1

SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

1TO1_DIFFPAIR

*

=STANDARD

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM


PHYSICAL

SPACING


D

SMBUS_SMC_A_S3_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_0_S0_SCL

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

7B5 7D5 42D2 7B5 7C5 42D2 42C2 42C2 42D5 42D5 7A7 42C5 42C5

42B5

y r

SMBus Charger Net Properties NET_TYPE ELECTRICAL_CONSTRAINT_SET

PHYSICAL

CHGR_CSI

1TO1_DIFFPAIR 1TO1_DIFFPAIR

CHGR_CSO

1TO1_DIFFPAIR 1TO1_DIFFPAIR

D

42B5

SPACING

CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N

a n i

C

C

m il

e r

B

P

A

B

SMC Constraints SYNC_MASTER=T18_MLB



DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 106

1

109

A

8

6

7

2

3

4

5

1

M97 SENSOR NET PROPERTIES TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

DIFFPAIR

*

=STANDARD

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM


PHYSICAL

SPACING


DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR

D

DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR

CHGR_CSO_R_P CHGR_CSO_R_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N ISNS_CPUVTT_P ISNS_CPUVTT_N ISNS_P1V5S0MCP_P ISNS_P1V5S0MCP_N ISNS_PVCORES0MCP_P ISNS_PVCORES0MCP_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P MCP_THMDIODE_N

44A8 57B3 44A8 57B3 45C5 45C5 10C6 45D5 10C6 45D5 44B7 44B7

D

44C7 44C7

y r 44D8

44D8 61C4

7C7 45B5 7C7 45B5

21C3 45C5 21C3 45B5

a n i

C

C

m il

e r

B

P

A

B

M97 SPECIAL CONSTRAINTS SYNC_MASTER=M97_MLB

A


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 107

1

109

8

6

7

2

3

4

5

1

M97 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS TABLE_BOARD_INFO

BOARD LAYERS

BOARD AREAS

BOARD UNITS (MIL or MM)

ALLEGRO VERSION

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA_P1MM

MM

15.5.1


SPACING_RULE_SET

LAYER


WEIGHT


NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE


DEFAULT

*

0.1 MM

?

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


STANDARD

*

=DEFAULT

?


BGA_P1MM

*

=DEFAULT

?


BGA_P2MM

*

=DEFAULT

?

*

*

BGA_P1MM

*

Y

=50_OHM_SE

0.100MM

30 MM

0 MM

0 MM

*

Y

=DEFAULT

=DEFAULT

12.7 MM

=DEFAULT

=DEFAULT

*

BGA_P1MM

BGA_P2MM

CLK_FSB

*

BGA_P1MM

BGA_P2MM

CLK_LPC

*

BGA_P1MM

BGA_P2MM

BGA_P3MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


*

=DEFAULT

?


WEIGHT

TOP,BOTTOM

Y

MEM_40S_VDD

BGA_P1MM

STANDARD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

CLK_PCI

*

BGA_P1MM

BGA_P2MM

CLK_PCIE

*

BGA_P1MM

BGA_P2MM

CLK_SLOW

*

BGA_P1MM

BGA_P2MM

TABLE_PHYSICAL_ASSIGNMENT_ITEM



DIFFPAIR NECK GAP

D


SPACING_RULE_SET


55_OHM_SE

STANDARD



MINIMUM LINE WIDTH

BGA_P1MM




MEM_40S

BGA_P1MM

MEM_CLK TABLE_SPACING_RULE_ITEM

DEFAULT

LAYER

PHYSICAL_RULE_SET

DIFFPAIR NECK GAP

STANDARD

PHYSICAL_RULE_SET

AREA_TYPE



D

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE




SPACING_RULE_SET

0.090 MM

LAYER

0.090 MM




55_OHM_SE

*

Y

0.076 MM

0.076 MM

=STANDARD

=STANDARD

1.5:1_SPACING

*

0.15 MM

?

2:1_SPACING

*

0.2 MM

?

y r TABLE_SPACING_ASSIGNMENT_ITEM

=STANDARD

FSB_DSTB

FSB_DSTB

BGA_P1MM



PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

50_OHM_SE

TOP,BOTTOM

Y

0.115 MM

0.115 MM

MAXIMUM NECK LENGTH



DIFFPAIR NECK GAP

2.5:1_SPACING

*

0.25 MM

?

3:1_SPACING

*

0.3 MM

?

4:1_SPACING

*

0.4 MM

?


WEIGHT ?




50_OHM_SE

*

Y

0.076 MM

0.076 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP




SPACING_RULE_SET

LAYER


40_OHM_SE

TOP,BOTTOM

Y


0.100 MM

0.165 MM

2X_DIELECTRIC

TOP,BOTTOM

0.140 MM

3X_DIELECTRIC

TOP,BOTTOM

0.210 MM

?

4X_DIELECTRIC

TOP,BOTTOM

0.280 MM

?

5X_DIELECTRIC

TOP,BOTTOM

0.350 MM

?

2X_DIELECTRIC

*

0.126 MM

?

a n i


40_OHM_SE

*

Y

0.126 MM

0.100 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP






27P4_OHM_SE

TOP,BOTTOM

Y

0.310 MM

0.310 MM

27P4_OHM_SE

*

Y

0.222 MM

0.222 MM



=STANDARD

=STANDARD

=STANDARD


3X_DIELECTRIC

*

0.189 MM

?

4X_DIELECTRIC

*

0.252 MM

?

5X_DIELECTRIC

*

0.315 MM

?




PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

70_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

70_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

Y

0.151 MM

0.100 MM

=STANDARD

0.224 MM

0.224 MM

70_OHM_DIFF

TOP,BOTTOM

Y

0.185 MM

0.100 MM

0.200 MM

0.200 MM

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

90_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

90_OHM_DIFF


Y

0.095 MM

0.095 MM

0.234 MM

0.234 MM

90_OHM_DIFF

TOP,BOTTOM

Y

0.112 MM

0.112 MM

0.220 MM

0.220 MM

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

100_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

100_OHM_DIFF


Y

0.075 MM

0.075 MM

0.244 MM

0.244 MM

100_OHM_DIFF

TOP,BOTTOM

Y

0.091 MM

0.091 MM

0.230 MM

0.230 MM

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH


DIFFPAIR NECK GAP

100_OHM_DIFF_HDD

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

100_OHM_DIFF_HDD


Y

0.083 MM

0.083 MM

0.400 MM

0.400 MM

100_OHM_DIFF_HDD

TOP,BOTTOM

Y

0.095 MM

0.095 MM

0.400 MM

0.400 MM

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH


DIFFPAIR NECK GAP



C












e r TABLE_PHYSICAL_RULE_ITEM



B

110_OHM_DIFF

*

N

=STANDARD

=STANDARD

110_OHM_DIFF


Y

0.075 MM

0.075 MM

=STANDARD

=STANDARD

=STANDARD

0.330 MM

0.330 MM



110_OHM_DIFF

TOP,BOTTOM

Y

0.077 MM

0.077 MM

PHYSICAL_RULE_SET

LAYER


MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

1:1_DIFFPAIR

*

Y

=STANDARD

=STANDARD

0.330 MM

0.330 MM


DIFFPAIR NECK GAP


A

MAXIMUM NECK LENGTH

P =STANDARD

0.1 MM

C

m il


MAXIMUM NECK LENGTH

BGA_P3MM


0.1 MM

B

M97 RULE DEFINITIONS SYNC_MASTER=M97_MLB

A


DRAWING NUMBER

D APPLE INC.

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7537

A

OF 109

1

109