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Mar 25, 2013 - Only bridge power / ground / IOs to C4 bumps. Side-by-Side Die Layout. ⢠Minimal heat flux issues. Pass
Heterogeneous 3-D stacking, can we have the best of both (technology) worlds
Liam Madden Corporate Vice President March 25th, 2013 © Copyright 2012 Xilinx .
The ‘Chameleon’ Chip Field Programmable Gate Array (FPGA)
Page 2
© Copyright 2012 Xilinx .
Moore’s Law 1965: Transistor density doubles every year 64K devices 10x doubling (actual 9X) 64 devices
10 years
Revised 1975: Transistor density doubles every two years
“Cramming more components onto integrated circuits” Gordon Moore, Electronics, Volume 38, Number 8, April 19th 1965 Page 3
© Copyright 2012 Xilinx .
A Career in One Graph Minimum Feature Size 1E-05 10um
1E-06 1um
1E-07 100nm
1E-08 10nm
1nm 1E-09 1979
Page 4
1981
1983
1985
1987
1989
1991
1993
1995
1997
© Copyright 2012 Xilinx .
1999
2001
2003
2005
2007
2009
2011
2013
Cost Comparison: Monolithic vs Multi-Die “Moore’s Law is really about economics” – Gordon Moore
Die Cost
Monolithic
Multi-Die
Die Area
Page 5
© Copyright 2012 Xilinx .
Why is First 3D Logic Product an FPGA?
Natural partition using “long lines” Very low “opportunity cost” No 3rd party dependence
“Size matters” to customers Compelling value proposition “next generation density in this generation technology”
Page 6
© Copyright 2012 Xilinx .
Virtex 2000T: Homogeneous Stacked Silicon Interconnect Technology (SSIT)
FPGA slice
Silicon Interposer >10K routing connections betweenSilicon slices Interposer ~1ns latency
FPGA Slices Side-by-Side
Page 7
© Copyright 2012 Xilinx .
Elements of SSIT FPGA Interposer
TSV C4
Microbumps 0.04mm Microbumps • Access to power / ground / IOs Through-silicon Vias (TSV) • Only bridge power / ground / IOs to C4 bumps
0.2mm Passive Silicon Interposer (65nm Generation) • 4 conventional metal layers connect micro bumps & TSVs
Side-by-Side Die Layout Package • Minimal heat flux issues Microbumps 28nm FPGA Slice
28nm FPGA Slice
28nm FPGA Slice
28nm FPGA Slice
New!
Silicon Interposer Through-Silicon Vias Package Substrate
1mm
Package Ball
Page 8
C4 Bumps BGA Balls
© Copyright 2012 Xilinx .
3D Supply Chain FPGA, Interposer, & Package Design
28nm FPGA & Interposer
Package Substrate IBIDEN
Bump, Die separation CoC/CoWoS, & Assembly
Final Test of Packaged Part
© Copyright 2012 Xilinx .
Co(CoS) Process Flow
Wafer with TSV u-pad/bump, Probe
Dice
Carrier
Carrier Mount Thin & TSV Reveal UBM & C4-bump
Interposer-on-Substrate
Carrier De-mount to Film frame
Page 10
Package
© Copyright 2012 Xilinx .
(CoW)oS Process Flow-1 (Courtesy of TSMC) Bottom die
Top-die
Stacking (μbump)
Wafer Molding
Carrier bonding carrier
B/S grinding
B/S C4 bumping Page 11
carrier
carrier © Copyright 2012 Xilinx .
(CoW)oS Process Flow-2 (Courtesy of TSMC) Transfer glass to tape
Tape carrier
Singulation Tape
TIS (Stacking, C4) Build up Subs.
Thermal Interface Metal (TIM) Lid Ring
TIS (Ring+Lid)
Top view
Page 12
Bottom view
© Copyright 2012 Xilinx .
Side view
3D Stacking: A world of difference
Virtex-7 2000T Interposer Area: ~775 mm2 Population: ~6.8 Billion Transistors Sub-chips: 5 Age: ~45 weeks
Earth Area: ~500 Million km2 Population: ~6.8 Billion People Oceans: 5 Age: ~4.5 Billion Years
© Copyright 2012 Xilinx .
Heterogeneous Integration
© Copyright 2012 Xilinx .
3 Decades of Microprocessor Integration A Personal History “Integrate or be integrated” – Fred Weber, former CTO AMD Year
Company
Product
Integration Level Core DP
1983
Harris
J11
1989
DEC
Rigel
1991
DEC
Alpha
2005
Microsoft
Xenon
2011
AMD
Fusion
Page 15
Ctl
L1 $
4um
1.5um
0.75um
3 Core
90nm
2 Core
40nm
© Copyright 2012 Xilinx .
L2$ FPU
North Bridge
GPU
What Happened to System on a Chip?
Logic
Memory
Analog
Global Revenue 2011
$150B
$68B
$45B
Moore Scaling
Good
Good
Poor
Technology “Vintage”
28nm
28nm
180nm?
High performance/ Low leakage
Low leakage/ moderate performance
Stable with good voltage headroom
>9
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