Factors for Choosing an SoC FPGA - Altera

Architecture Brief

Factors for Choosing an SoC FPGA Introduction Basing a system on silicon with a strong architecture is key to ensuring that your design meets its performance requirements now and into the future. There are advantages to using an SoC FPGA rather than an FPGA and separate microprocessor, also, there are clear advantages compared to an ASIC, as well as advantages over using stand-alone microprocessors or high-end microcontrollers in systems. This Architecture Brief presents design considerations as to how an SoC FPGA can meet a system design’s requirements, technically and commercially. Key aspects of this Architecture Brief are highlighted in an online video: “I’m interested in using an SoC FPGA, how do I decide which one to choose?” which can be found at www.altera.com/socarchitecture.

Types of Current Implementations to Consider SoC FPGAs can be easily be considered for designs that already use an FPGA and separate microprocessor. SoC FPGAs provide comparable or increased functionality and performance coupled with board space, power and system cost savings. For replacing proprietary ASICs which include a microprocessor, an SoC FPGA delivers a fully-functional, fully-compatible, high performance dual-core ARM Cortex-A9 processor, running at up to 1GHz with today’s 28nm process technology. There are also no expensive mask changes or minimum purchase requirements, no manufacturing lead time, lower reprogramming risk and no additional licensing or royalty payment for the embedded processor, high-speed transceivers or other advanced system technology associated with SoC FPGAs. Systems that typically use stand-alone microprocessors or high-end microcontrollers may still benefit from SoC FPGAs. Rather than settle for an off-the-shelf processors that only approximately fits the application, maybe selecting a processor that is missing an Ethernet port, USB channels or interrupt lines, for example, SoC FPGAs offer the advantage that a custom ARM microprocessor derivative can be created—instantly, right on the desktop. Now, system designs do not have to accept compromises due to the lack of off-the-shelf processor derivatives, the design can be differentiated both in hardware and software, making it more difficult for competitors to copy or emulate.

How to Choose the Right SoC FPGA for a Specific Application At first glance, the programmable SoC offerings in Table 1 from various vendors might appear similar.

Table 1: Commercially-Available SoC FPGAs Altera SoC FPGAs

Xilinx Zynq-7000 EPP

Microsemi SmartFusion2

ARM Cortex-A9

ARM Cortex-A9

ARM Cortex-M3

Processor Class

Application processor

Application processor

Microcontroller

Single or Dual Core

Single or Dual

Dual

Single

Processor Max. Frequency

1.05 GHz

1.0 GHz

166 MHz

L1 Cache

Data: 32 KB Instruction: 32 KB

Data: 32 KB Instruction: 32 KB

No data cache Instruction: 8 KB

L2 Cache

Unified: 512 KB, with error correction code (ECC)

Unified: 512 KB

Not available

Memory Management Unit (MMU)

Yes

Yes

Yes

Floating-Point Unit/NEON™ Multimedia Engine

Yes

Yes

Not available

Acceleration Coherency Port (ACP)

Yes

Yes

Not available

Processor

Interrupt Controller

Generic (GIC)

Generic (GIC)

Nested, vectored (NVIC)

On-Chip Processor RAM

64 KB, with ECC

256 KB, no ECC

64 KB, no ECC

Direct Memory Access Controller

8-channel ARM DMA330 32 peripheral requests (FPGA + hard processor system)

8-channel ARM DMA3304 peripheral requests (FPGA only)

1-channel HPDMA 4 requests

External Memory Controller

Yes

Yes

Yes

Memory Types Supported

LPDDR2, DDR2, DDR3L, DDR3

LPDDR2, DDR2, DDR3L, DDR3

LPDDR, DDR2, DDR3

External Memory ECC

16 bit, 32 bit

16 bit

8 bit, 16 bit, 32 bit

External Memory Bus Max. Frequency

400 MHz (Cyclone® V SoC), 533 MHz (Arria® V SoC)

533 MHz

333 MHz

Processor Peripherals

1x quad SPI controller with 4 chip selects

1x quad SPI or dual quad SPI controller with 2 chip selects

1x 10/100/1G Ethernet controller

1x NAND controller (single- and multilevel cell - MLC or SLC)

x static memory controller (NAND-SLC, NOR, or SSRAM)

2x USB 2.0 OTG controller 2x UART



2x USB 2.0 On-the-Go (OTG) controller

2x USB 2.0 OTG controller 2x SD/ SDIO controller

2x I2C controller 1x CAN controller 2x SPI

1x SD/MMC/SDIO controller 2x UART 4x I2C controller 2x CAN controller 2x SPI master, 2x SPI slave controller 4x 32 bit general-purpose timers 2x 32 bit watchdog timers

2x UART 2x I2C controller 2x CAN controller

2x general-purpose timers 1x watchdog timer 1x real-time clock (RTC)

2x SPI controllers (master or slave) 2x 16 bit triple-mode timer/counters 1x 24 bit watchdog timer

FPGA Fabric

Cyclone V, Arria V

Artix-7, Kintex-7

Fusion2

FPGA Logic Density Range

25 K to 462 K LE

28 K to 444 K LC

6 K to 146 K LE

Hardened Memory Controllers in FPGA

Up to 3, with ECC

Not available

Not available

High-speed Transceivers

Available at all densities

Higher-density devices only

Higher-density devices only

Analog Mixed Signal (AMS)

Not available

2 x 12-bit, 1 MSPS analog-to- digital converters (ADCs)

Not available

Boot Sequence

Processor first, FPGA first, or both simultaneous

Processor first

Processor boot, FPGA non- volatile

They all integrate an ARM processor, various peripherals, and an FPGA into a single device. In practice, however, it is critical to closely evaluate these offerings, and look deeper than the data sheet. The underlying architecture and its implications must be evaluated relative to a specific application. Closer examination and consideration reveals many significant differences at an architectural level. The selection criteria centers on these six areas: • System performance • System reliability and flexibility • System cost • Power consumption • Development tools • Future roadmap

Altera SoC Features and Benefits Altera SoCs integrate an ARM-based hard processor system (HPS), consisting of processor, peripherals, and memory interfaces, with the FPGA fabric using a high-bandwidth interconnect backbone. They combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable ARM-based SoCs are ideal for: • Reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA • Improving system performance via high-bandwidth interconnect between the processor and the FPGA • Differentiating the end product by customizing in both hardware and software • Developing ARM-compatible software with unmatched target visibility, control, and productivity using Altera’s exclusive FPGA-adaptive debugging These devices include additional hard logic such as PCI Express® Gen2, multi-port memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers. ARM-compatible software with unmatched target visibility, control, and productivity, using Altera’s exclusive FPGA-adaptive debugging, are also features. The SoC FPGA also offers independent processor boot / FPGA configuration and the FPGA operates even if the CPU resets. There is the option for shared or independent memories to increase system flexibility.

Architecture Matters Altera’s SoCs for embedded systems are a solid foundation that bring to the design: • Improved system performance through a higher HPS to FPGA bandwidth interconnect, hardware acceleration, and increased memory performance. SoC FPGAs deliver 4,000 DMIPS for under 1.8W, 1,600 GMACs, 300 GFLOPS DSP performance and a maximum of over 125Gbps processor to FPGA interconnect for fast, efficient data transfers. • Increased reliability through Error Correction Code (ECC) functionality is built into the SoC FPGA for numerous memory and peripheral interfaces to protect the data throughout the data transfer path, not just the main system memory interface. The Memory Protection Unit is integrated in the DRAM controller to protect against potential hardware or software errors. • More flexibility through hardware differentiation, system boot and configuration options, and multiple hardened memory controllers. Warm or cold CPU reset that initiates without affecting or reprogramming the FPGA unless selected by the designer. • Lower system cost can be realized through single and dual core variants, a wide single-chip integration and range of densities, and integrated hard IP such as a PCIe® controller. Additionally, SoC FPGAs can save up to 30% of the power budget, compared to a two-chip solution. Another benefit is that there is no need for external power-off sequencing circuitry. • Increased productivity is provided through the Altera FPGA-adaptive debugging tool. This system debug approach supports software, hardware and FPGA. Data can be added to any master to trace, and trace data can be streamed to any slave for unmatched target visibility, control, and productivity • Path for the future with SoC FPGAs built on leading-edge process technologies: TSMC 28 and 20nm and Intel 14nm tri-gate. The Altera roadmap provides solutions for high-end, mid-range, and low-end applications, forward migration of software, and products with average life cycles of 15 years or more.

Conclusion

Want to Dig Deeper?

After consideration of design criteria and functionality requirements, a system design engineer can implement an SoC FPGA to benefit from increased reliability, power and cost reductions as well as future-proofing the design for in-the-field upgrades and to respond rapidly to the market’s changing needs, without penalties or limitations associated with conventional architectures.

Check out the Altera SoC Product Brochure at http://www.altera.com/literature/br/br-soc-fpga.pdf for an overview of Altera’s SoC FPGA product offering

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