History of Processor Performance

History of Processor Performance

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Abstract Stages of Execution Instruction Fetch (Instructions fetched from memory into CPU)

Instruction Issue / Execution (Instructions executed on ALU or other functional unit)

Instruction Completion / Commit (Architectural state updated, i.e., regfile or memory)


Multiple Instruction Issue Processors Multiple instructions fetched, executed, and committed in each cycle

In superscalar processors instructions are scheduled by the HW

In VLIW processors instructions are scheduled by the SW

F: E: C:

F: E: C:

In all cases, the goal is to exploit instruction-level parallelism (ILP) 5 Tuesday, April 24, 12

Flynn’s Taxonomy Single Instruction, Single Data (SISD)

Single Instruction, Multiple Data (SIMD)

Multiple Instruction, Single Data (MISD)

Multiple Instruction, Multiple Data (MIMD)

Exploits instr-level parallelism (ILP)

Exploits data-level parallelism (DLP) 6 Tuesday, April 24, 12

Out-of-order execution In in-order execution, instructions are fetched, executed, and committed in compiler order

In out-of-order execution (OOO), instructions are fetched, and committed in compiler, order; may be executed in some other order

F:

F:

E:

E:

One stalls, they all stall Relatively simple HW

C:

C:

One stalls, independent instrs may proceed Additional hardware required for reordering

Another way to exploit instruction-level parallelism (ILP) 7 Tuesday, April 24, 12

Speculation Speculation is executing an instruction before it is known that it should be executed Speculate

If correct

If incorrect

F:

F:

F:

E:

E: E:

C:

C:

Misspeculation executes excess instructions, costing time and power

C:


Performance

The Memory Wall

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A result of this gap is that cache design has increased in importance over the years. This has resulted in innovations such as victim caches and trace caches. 9 Tuesday, April 24, 12

Modern Processor Performance While single threaded performance has leveled, multithreaded performance potential scaling.


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Area

Performance

Power

MIPS/Watt (%)

4

Increase

3


2 1 0

Pipelined

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Superscalar

OOO-Speculation

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The Power Wall

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Much of it goes back to the transistor

Source: Intel press foils Tuesday, April 24, 12


individual atoms! Source: Intel press foils Tuesday, April 24, 12


individual atoms! = leakage current + defects Tuesday, April 24, 12

Source: Intel press foils

A model of power

P = Pswitch + Pleakage Pswitch = Eswitch x F = Pleakage = Vdd x I Tuesday, April 24, 12

2

(C x Vdd ) x F

Voltage Scaling: DVFS + Near-Threshold Computing

[Source: Dreslinski et al.: Near-Threshold Computing: Recplaiming Moore’s Law Through Energy Efficient Integrated Circuits] Tuesday, April 24, 12

Voltage Scaling: DVFS + Near-Threshold Computing

[Source: Dreslinski et al.: Near-Threshold Computing: Recplaiming Moore’s Law Through Energy Efficient Integrated Circuits] Tuesday, April 24, 12

Power Density (Watts/cm2)

Chip Area and Power Consumption 1500 Active Power Leakage Power 1000

With leakage power dominating, power consumption roughly proportional to transistor count

power envelope to remain constant

500

0 90nm

65nm

45nm

32nm

22nm

16nm

Source: Shekhar Borkar (Intel)

Integer Performance

1000

100

Pollack’s Law: Processor performance grows with sqrt of area

10

1 1

10

100

1000

10000

100000

Processor Area

Source: Shekhar Borkar (Intel) Tuesday, April 24, 12

The Resulting Shift to Multicore

Perf = 1 Power = 1

Tuesday, April 24, 12


Perf = 1 Power = 1


Perf = 2 Power = 4


Perf = 1 Power = 1


Perf = 2 Power = 4

Perf = 4 Power = 4

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x86 64-bit Architecture Evolution 2005

AMD Opteron™

2010

2007

2008

AMD Opteron™

“Barcelona”

“Shanghai”

“Istanbul”

“Magny-Cours”

90nm SOI

90nm SOI

65nm SOI

45nm SOI

45nm SOI

45nm SOI

K8

K8

Greyhound

Greyhound+

Greyhound+

Greyhound+

L2/L3

1MB/0

1MB/0

512kB/2MB

512kB/6MB

512kB/6MB

512kB/12MB

Hyper Transport™ Technology

3x 1.6GT/.s

3x 1.6GT/.s

3x 2GT/s

3x 4.0GT/s

3x 4.8GT/s

4x 6.4GT/s

Memory

2x DDR1 300

2x DDR1 400

2x DDR2 667

2x DDR2 800

2x DDR2 1066

4x DDR3 1333

Mfg. Process

2003

2009

CPU Core

Max Power Budget Remains Consistent 3 | The AMD “Magny-Cours” Processor | Hot Chips | August 2009

[Source: HotChips ‘09] Tuesday, April 24, 12

19

Tick%Tock'Development'Model Merom

Penryn

Nehalem

Westmere

Sandy Bridge

NEW

NEW

NEW

NEW

NEW

Process

Microarchitecture

Process

Microarchitecture

65nm

45nm

45nm

32nm

32nm

TOCK

TICK

TOCK

TICK

TOCK

Microarchitecture

1

Forecast

Nehalem-EX Architecture 6

All products, dates, and figures are preliminary and are subject to change without notice.

Hot Chips 2009

[Source: HotChips ‘09] Tuesday, April 24, 12

20

Nehalem'Core/Uncore'Modularity C O R E

C O R E

…

C O R E

Core

L3 Cache

DRAM

…

IM C

QPI

… QPI

Power & Clock

Uncore

QPI

…

Common%core%for%client%and%server%CPUs – http://www.intel.com/technology/architecture