MIRTHE general aspects - Cordis

Monolithic InP‐based Dual Polarization QPSK Integrated Receiver and Transmitter for CoHerent 100‐400Gb/s Ethernet

MIRTHE

Concertation Meeting Brussels, 20 October 2010 MYRTHE, MYRTLE, MYRTE

christophe.kazmierski@3‐5lab.fr

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http://www.ist‐mirthe.eu

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Project motivation and challenges New low environmental footprint scalable technology for 100‐400Gb/s transmissions

MIRTHE concept applies to metro, long haul and could have impact on access in the future

• Reduction of cost and power consumption of 100GbE transmission equipment, • Increasing the bit rate to 100 G and higher, while still staying within a given 50 GHz‐grid • Need of future‐proof component technologies for next generation terabit networks


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Objectives


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Complementary partnership - EAM-based optoelectronic devices (ATL) - Very high-speed waveguide-integrated photodetectors and passive components (HHI) - Packaging of high-speed optoelectronics (U2T) - Coherent DP-QPSK (ALBL) - Modelling software for advanced device and modulation schemes (VPI) - Accurate simulation and design of waveguide based photonic integrated circuits (UMA)

EU expertise

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Rx circle HHI, U2T, UMA, VPI

Tx circle ATL, U2T, VPI

Module circle U2T, ATL, HHI Specifications, scenarios, testing, modelling circle ALBLF, VPI, U2T, HHI


WP4 PIC2PIC evaluation 5

Beyond state‐of‐the‐art Small size QPSK/QAM TX chips based on novel phase switching in EAM‐ based PICs

Fully integrated RX chips demultiplexing both polarizations (DP/PDM‐ QPSK),

Evaluation of novel monolithic coherent receiver types, applying multiport approaches

Demonstration of low‐power low‐footprint multi‐level coding TX and RX packages

Demonstration of 200 – 400 Gb/s capability of InP‐based TX and RX PICs Integrated approach for photonic circuit numerical modelling and design


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Expected impact Communication sector: Increase the data rate but also fit within small channel spacing while still improving the network throughput by one order of magnitude at least Industrial competitiveness: cost effectiveness and reduced power/bit of future data transport network by offering a solution an integrated approach for TX and RX front ends future proof solutions for an increased bit rate (up to 400Gb/s) in line with the expected future evolution of Si ADC technology connection with Standardization bodies through Alcatel‐Lucent (ITU‐T and IEEE) and U2T (OIF) Social impact: more citizens to access broadband networks increasing their communication throughput reducing the environmental footprint of ICT equipment christophe.kazmierski@3‐5lab.fr

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TX InP‐PIC technologies QPSK 50 Gb/s OFC2010, I.Kang

Novel concept for QPSK/QAM generation

Innovative active‐passive integration technology using selective epitaxy christophe.kazmierski@3‐5lab.fr

Bloc diagram of TX PIC

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RX InP‐PIC technologies Full integration of novel polarization management and two coherent QPSK receivers on a single InP‐PIC

ECOC2010, J. K. Fischer

High sensitivity, high speed performance (160Gb/s)


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Packaging technologies OIF recommendation for QPSK Tx


Example of Integrated DPSK‐Receiver (IDRV)

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Modelling and Testing

From actual PIC component modeling to realistic transmission evaluations PDM QPSK test bed


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4‐step workflow roadmap By the end of year 1, single polarization 28 GB prototypes will be available 1 year later, the dual polarization prototypes will be demonstrated, operating at 28 GB (112 Gb/s) By Month 33, the packaged DP‐QPSK TX and RX will be available working at 56 GB (224 Gb/s) A final ambitious step (end of MIRTHE) will see the 400 Gb/s demonstration, based on 16 QAM format and multi‐ level drivers.


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