Model Based System Engineering at Lockheed Martin MS2 - IBM

Model Based System Engineering at Lockheed Martin MS2 IBM Seminar on Hardware/Software Co-design December 9th, 2010

Bill Gnadt, Ph.D. Lockheed Martin – Mission Systems & Sensors Syracuse, New York [email protected] 1

Lockheed Martin Corporate Structure

Aeronautics

Electronic Systems

Information Systems & Global Services

Space Systems

Mission Systems & Sensors (MS2) Syracuse, NY

© COPYRIGHT LOCKHEED MARTIN 2010

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How We Bring it Together to Meet Customer Needs Open Business Partnerships

CMMI Systems Engineering, Integration, and Management Processes

Industry

LM Corporation

Mission Systems & Sensors (MS2)

Functional and Physical Allocation Synthesis, Design, and Validation System Performance Analysis

Tech Refresh

Government Labs and Academia

Optimized Customer-Centric Resources

Requirements Definition and Analysis

“Best in Class” System-of-Systems Solutions

Program Management Global Sustainment

Engineering Design Challenges Remain for Complex Systems © COPYRIGHT LOCKHEED MARTIN 2010

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Model-Based Systems Engineering Method • We use SysML and SystemC as part of a larger effort to demonstrate the Model Based System Engineering Method (MSEM) – To provide unimpeded, undistorted communication between systems, software and hardware engineers within an engineering team – To realize cost savings, schedule reduction and risk reduction through model based design • To that end, the techniques applied in MSEM inter-connect – Requirements – Hardware Architecture – Model Development – Simulation Results SystemC Models Describe an Executable Specification for Development of a Design Baseline © COPYRIGHT LOCKHEED MARTIN 2010

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Engineering Design Methodology Customer Input

LM IP & Innovation

MSEM Solution

Existing Tools

Concept Level Design

Systems Engineering

DOORS, Excel

Disconnect

Design Refinement

SysML

Matlab, C++, Java

Module Development

HW/SW Partitioning

Hardware Design

SystemC

Software Design

Disconnect

VHDL

Disconnect

C/C++

MSEM Can Increase Efficiency and Streamline the Delivery of Innovative Solutions to the Customer © COPYRIGHT LOCKHEED MARTIN 2010

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Pilot Project Objectives Complete Hardware Design

• Develop a System-Level Model and Refine to the Element Level (IBM Rational Rhapsody) • Auto-Generate SystemC Reference Model (ExperMeta MetaSyn) • Apply Behavioral Synthesis Tool (AutoESL AutoPilot) • Target Altera Hardware (Altera Quartus) • Verify Performance Estimates

Initiator

Sensor

48x 10 GigE

Packet Router Target Hardware Transceiver Signal Integrity Development Kit Stratix IV GX Edition

40x 10 GigE Hardware Subset

Signal Processor

Target

Confirm Accuracy of Performance Estimates at SysML, SystemC, VHDL and Hardware Level © COPYRIGHT LOCKHEED MARTIN 2010

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Overall Team Approach Team Members

ExperMeta •Sandeep Desai •Allen Goldberg

AutoESL

Altera

•Jerry Philippe •Duncan Mackay

•Gary Gavenda •Bob Spurr

Clarkson University •Bob Meyer •Abul Khondker •Susan Conry •Tim Fanelli

Tool Flow

MetaSyn SysML

AutoPilot SystemC

Quartus

Altera Hardware

VHDL

ModelSim

Teammates Contributed Resources and Expertise to Achieve Project Objectives © COPYRIGHT LOCKHEED MARTIN 2010

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Modeling Assumptions • Base Design on Packet Router Requirements – Number of Interfaces – Communication Protocols

• Capture Design in SysML, Synthesize SystemC (ExperMeta) • Synthesize VHDL, Target Hardware (Clarkson University) • Share Artifacts and Methodology Packet Producer

Packet Router

Packet Consumer

Modeling Simplifications Ease Tool Integration While Demonstrating Key Concepts © COPYRIGHT LOCKHEED MARTIN 2010

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SysML for System Specification Execution • Kahn Process Network • Actor model • Communication-centric Structure • modules • ports • interfaces Behavior •Statecharts

Connections to requirements and other specification artifacts


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HW/SW System Workflow refine

Automation GAP!

generate

co-execution & validation

Hardware: SystemC, HDL, …

GDSII

Software: C/C++

SystemC

Rhapsody: UML/SysML

HDL

import

Verification

DOORS: Requirements

Electronic Design Level Tool Chain Transaction Level


Cycle-Accurate

Register Transfer Level Netlist

Placement Routing

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Synthesizable SystemC Design Captured in SysML and SystemC Synthesized from MetaSyn

This Simplified Model Demonstrates Key Aspects of Methodology


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Design of simple packet send/receive system in Altera’s Quartus II Design Automatically Synthesized from AutoPilot

NiOS Processor © COPYRIGHT LOCKHEED MARTIN 2010

Packet pipe 12

NioS II Based Controller C-code for Testing the Packet Pipe Console Output

Source Code


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Detailed Simulation of Packet Pipe

ModelSim Output

Altera FPGA Signal Tap


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Hardware Design Impact Hardware/Software Co-Design System Model

SysML

Hardware/Software Co-design

Software Model

Hardware Model

UML

Tool

SysML/UML

Process

Rhapsody

Pilot Focus

Rhapsody (Connect Set)

Tool

C++ Code Generation

ExperMeta MetaSyn Virtual Prototyping

Software Simulation

Process SysML-SystemC Synthesis

Hardware Simulation

SystemC

SystemC AutoESL AutoPilot

SystemC-RTL Synthesis

RTL HandCoding

VHDL

Altera Quartus

SystemC-Tactical Code Translation

Logic Synthesis

Netlist EDIF Place and Route

General-Purpose Computing Hardware

I&T

FPGA Hardware Bitstream

C/C++


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Next Steps • Successful flow of a simple design from – SysML to – SystemC to – VHDL to – Realization in FPGA hardware • Verification at hardware level using Nios processor to exercise hardware units • Improved integration between tool vendors: IBM, ExperMeta, AutoESL and hardware vendors: Xilinx and Altera (IP) • Demonstrated success on a realistic problem set – Seek to exercise broad range of tool functionality • Further Metric Collection Methodology and Tools will Eventually be Ready for LargerScale Applications © COPYRIGHT LOCKHEED MARTIN 2010

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Questions?

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BACKUP

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Lockheed Martin Locations

(http://www.lockheedmartin.com/data/assets/corporate/documents/Locations-Map.pdf)


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Altera Quartus Tool Flow From AutoPilot

To ModelSim

To FPGA Hardware


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Abstract “Model Based System Engineering at Lockheed Martin MS2” We use SysML and SystemC as part of a larger effort to demonstrate the Model Based System Engineering Method (MSEM). The primary goal of MSEM is to provide unimpeded, undistorted communication between Systems, Software and Hardware engineers within an engineering team. A secondary goal is to show cost savings, schedule reduction and risk reduction. To that end, the techniques applied in MSEM link requirements, hardware architecture, model development and results. First, a system level model is designed and captured in SysML, a systems modeling language. Next, a SystemC model captures hardware functionality into an “executable specification”, leading to a design baseline. For this project, MSEM techniques are applied to the development of a high-speed packet router using FPGA hardware. Current accomplishments include: accurate prediction of hardware performance using SystemC, application of Rhapsody to support automatic generation of SystemC code and FPGA hardware descriptions. A future goal involves interfacing a SystemC hardware model with tactical software for accurate interface verification.


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