Multiple timing list arrangement

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Jan 4, 1972 - processor scratch pad memory for storing data needed by the processor to .... by the present pointer if th
United States Patent Inventor

"113,633,181

Michael F. Sikorsky

[56]

Neptune City, NJ. Appl. No. 887,5 1 7 Filed Dec. 23, 1969 Patented Jan. 4, 1972

Assignee

References Cited

OTHER REFERENCES The Bell System Technical Journal, Volume 43. number 5,

September 1964, TKLB435, by American Telephone and

Bell Telephone Laboratories, Incorporated Murray Hill, Berkeley Heights, NJ.

Telegraph Company, pp‘ 1850— 1891 and 1926— 1959. Primary Examiner-Raulfe B. Zache Assistant Examiner-J an E. Rhoads

Attorneys—R. J. Guenther and James Warren Falk

[54] MULTII'LE TIMING LIST ARRANGEMENT 7 Claims, 7 Drawing Figs. [52] US. Cl ...................................................... .. 340/ 172.5 [51] Int. Cl .................................................. .. G06f 7/02,

[50]

G06f 9/ 1 8, G06f 15/46 Field of Search .......................................... .. 340/1725; ‘

235/ 151.3

ABSTRACT: A program controlled timing arrangement for service circuit registers in a real-time processing system is dis closed. Sixty timing lists and a modulo-60 counter for indexing the lists are provided. At l-second intervals the registers on the list presently indexed by the counter are examined for timeout and the counter is incremented. A register requiring timing is placed on a list in accordance with the required time interval and the calculated value of the counter at the termina tion of this interval. Facilities are also provided for interrupt

ing and reinitiating timing without loss of unelapsed time.

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ADDRESS OF FIRST REGISTER ——————————————————— ——

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FOR INTERVAL o TIMING LIST

ADDRESS OF LAST REGISTER ADDRESS OF FIRST REGISTER

FOR INTERVAL ,

ADDRESS OF LAST REGISTER

TIMING LIST

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