Title (Verdana Bold 18pt)

5 downloads 158 Views 3MB Size Report
Sep 1, 2010 - Bringing The Best of Both Together. Windows ... programming and memory ... Desktop. Enthusiast. Server. 4P
CPU / GPU Industry Dynamics and Technologies Chekib Akrout, Senior Vice President, AMD September 1, 2010

Agenda

• AMD Today • New x86 Innovations • Foundry Requirements • 32nm Update

2

AMD the Design Company

Only two companies develop and deliver x86 processors in volume

Only two companies develop and deliver leading-edge 3D graphics

Only AMD does both 3

Bringing The Best of Both Together x86 CPU owns the Software World

GPU Optimized for

Windows, MacOS and Linux franchises

Enormous parallel computing capacity

Thousands of apps

Outstanding performance-per watt-per-dollar

Established programming and memory model Mature tool chain Extensive backward compatibility for applications and OSs High barrier to entry

4

Modern Workloads

Very efficient hardware threading SIMD architecture well matched to modern workloads: video, audio, graphics

Why AMD Fusion?

5

Sources: YouTube online fact sheet, retrieved December 7, 2009 http://www.youtube.com/t/fact_sheet; CEA Market Research Report – Amassing Digital Fortunes: A Digital Storage Study, MAY 2008

A New Era of Processor Performance Single-Core Era

Constrained by: Power Parallel SW availability Scalability

we are here

Time

we are here

Time (# of processors)

Enabled by:  Abundant data parallelism  Power efficient GPUs Constrained by: Programming models

Targeted Application Performance

?

Throughput Performance

Single-thread Performance

Constrained by: Power Complexity

6

Heterogeneous Systems Era

Multi-Core Era

we are here

Time (Data-parallel exploitation)

Entering the AMD Fusion Processor Era APU:  Combination of CPU and programmable GPU architectures for high-performance heterogeneous compute capability  High-speed bus architecture  Shared, low-latency memory model  Single die design  AMD‟s first APU, “Ontario”, expected in market early 2011

7

Agenda

• AMD Today • New x86 Innovations • Foundry Requirements • 32nm Update

8

Two x86 Cores Tuned for Target Markets Mainstream Client and Server Markets

“Bulldozer” Performance & Scalability

“Bobcat” Flexible, Low Power & Small

9

Low Power Markets

Small Die Area

Cloud Clients Optimized

The “Bobcat” Core Architecture  Sub one-watt capable core  Out-of-order execution engine  Synthesizable / Easy to Reuse  Complete ISA support



SSE1-3 and virtualization

 90% of today‟s mainstream performance in less than half of the silicon area*  2011 notebook “Ontario” APU on 40nm bulk silicon from TSMC 10

* Based on internal AMD modeling using benchmark simulations

The “Bulldozer” Core Architecture  An innovative design that delivers true core functionality by pairing two dedicated integer execution cores with a shared floating-point unit  Second integer unit is only 12% of the total core design  Estimate up to 50% more server performance from 33% more cores compared to “Magny-Cours”*  Drop-in upgrade into existing server infrastructure planned for 2011

11

* Based on internal AMD modeling using benchmark simulations

Agenda

• AMD Today • New x86 Innovations • Foundry Requirements • 32nm Update

12

Power

Different Technology Needs Server 4P Desktop Enthusiast

Server 1P and 2P

Desktop

Mobile

Mainstream / Value

Mobile Netbook

13

Mobile Ultra-Thin

Desktop

Replacement

Mainstream

Performance

AMD Fusion Requirements for Foundries

CPU  Low Latency  Broad voltage requirements  Graduated metal stack  Higher frequency  Power Reduction

14

GPU Process Technology That Supports Needs of 32nm Both “Llano” APU

    

High Bandwidth Low voltage focus Dense metal stack Parallelized structures Power Reduction

Agenda

• AMD Today • New x86 Innovations • Foundry Requirements • 32nm Update

15

32nm Description • Gate First, HKMG technology developed and manufactured by GLOBALFOUNDRIES

• Dual-oxide, 3-Vt SOI devices utilizing stress technology for enhanced performance • „Graduated‟ 11-layer metal stack with low-k layers to reduce RC and overall capacitance • Variety of High-Density SRAM cells support both large caches and embedded compiled RAMs in the GPUs

• Dedicated components to enable Analog/Phy circuitry (resistors, AVT transistors, eFuses, diodes)

16

32nm HKMG / Fmax distribution Expected median

N+6

N+4

N+2

N

N-2

N-4

N-6

N-8

N-10

17

Challenges and Opportunities • Continue to push density – Graphics has an insatiable demand for compute power  Solve the performance problem together – power density has been slowed by VDD non-scaling

• Unlock benefits of TSV/Die Stacking  We need a vision for which technologies to invest in as an industry:

– FinFET – Dense Memory – Photonics

18

Voltage limit trends 1.6 1.4

1.2 1 Vmin

0.8

Vmax_FEOL

0.6

Vmax_BEOL

0.4 0.2 0 90nm

65nm

45nm

32nm

22nm

15nm

Die Stacking  The industry is on the horizon of stacked die products

200

5

160

4

120

3

80

2 Compute Power

40

System Power

1

Performance 0

0

1

1.5

19

2

2.5

Year

3

3.5

4

4.5

Relative Performance

Power

 The benefit is power reduction in both components and systems

32nm Orochi Die

20

Summary:  AMD as a design company is solidly positioned with its IP offerings  Chip architectures and software are evolving to address visual computing / graphically rich environments  The APU addresses that market need  Close foundry partnerships are critical to address evolving process technology requirements

21

Thank-You

22

Disclaimer & Attribution DISCLAIMER The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION 2010 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo,, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

23