TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL ...

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

D D

D

Direct Upgrades to TL07x and TL08x BiFET Operational Amplifiers Faster Slew Rate (20 V/µs Typ) Without Increased Power Consumption TL051 D OR P PACKAGE (TOP VIEW)

OFFSET N1 IN– IN+ VCC–

1

8

2

7

3

6

4

5

NC VCC+ OUT OFFSET N2

On-Chip Offset-Voltage Trimming for Improved DC Performance and Precision Grades Are Available (1.5 mV, TL051A)

TL052 D, P, OR PS PACKAGE (TOP VIEW)

1OUT 1IN– 1IN+ VCC–

1

8

2

7

3

6

4

5

VCC+ 2OUT 2IN– 2IN+

TL054 D, DB, N, OR NS PACKAGE (TOP VIEW)

1OUT 1IN– 1IN+ VCC+ 2IN+ 2IN– 2OUT

1

14

2

13

3

12

4

11

5

10

6

9

7

8

4OUT 4IN– 4IN+ VCC– 3IN+ 3IN– 3OUT

description/ordering information The TL05x series of JFET-input operational amplifiers offers improved dc and ac characteristics over the TL07x and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. Texas Instruments improved BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade existing circuits or for optimal performance in new designs. BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption. The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers. Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input voltage limits and output swing when operating from a single supply. DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies. The TL05x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

ORDERING INFORMATION TA

VIOmax AT 25°C PDIP (P)

Tube of 50

800 µV SOIC (D)

0°C to 70°C

1.5 mV

4 mV

800 µV

TL051ACP

TL051ACP

TL052ACP

TL052ACP

TL051ACD

051AC

Tube of 75

TL052ACD

Reel of 2500

TL052ACDR

052AC

TL051CP

TL051CP

TL052CP

TL052CP

Tube of 25

TL054ACN

TL054ACN

Tube of 75

TL051CD

Reel of 2500

TL051CDR

Tube of 75

TL052CD

Reel of 2500

TL052CDR

Tube of 50

TL054ACD

Reel of 2500

TL054ACDR

SOP (PS)

Reel of 2000

TL052CPSR

TL052

SSOP (DB)

Reel of 2000

TL054CDBR

TL054

PDIP (N)

Tube of 25

TL054CN

TL054CN

Tube of 50

TL054CD

Reel of 2500

TL054CDR

SOP (NS)

Reel of 2000

TL054CNSR

TL054

PDIP (P)

Tube of 50

TL052AIP

TL052AI

Tube of 75

TL052AID

Reel of 2500

TL052AIDR

Tube of 25

TL054AIN

TL054AIN

TL051IP

TL051IP

TL052IP

TL052IP

Tube of 75

TL051ID

TL051I

Tube of 75

TL052ID

Reel of 2500

TL052IDR

Tube of 50

TL054AID

Reel of 2500

TL054AIDR

Tube of 25

TL054IN

Tube of 50

TL054ID

Reel of 2500

TL054IDR

Tube of 50

PDIP (N)

SOIC (D)

SOIC (D)

SOIC (D)

PDIP (P)

Tube of 50

1 5 mV 1.5 SOIC (D)

PDIP (N) 4 mV

TOP-SIDE MARKING

Tube of 75

PDIP (P)

PDIP (N)

–40°C 40°C to 85°C

ORDERABLE PART NUMBER

PACKAGE†

SOIC (D)

TL051C TL052C TL054C

TL054C

052AI

TL052I TL054AI TL054IN TL054I

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

symbol (each amplifier) IN–

– OUT +

IN+

equivalent schematic (each amplifier) VCC+

Q10 Q2

Q15 Q3

JF3

Q7 Q16

Q6 Q13

Q11 IN+

R7

Q12

D1 IN– JF1

R9 OUT

R5

JF2

R8 C1

Q4

Q14

Q1 See Note A

Q9

Q5

OFFSET N1 OFFSET N2

R10

R4 R1

Q17

Q8

R2

D2

R6

R3

VCC– NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x. ACTUAL DEVICE COMPONENT COUNT† TL051

TL052

TL054

Transistors

COMPONENT

20

34

62

Resistors

10

19

37

Diodes

2

3

5

Capacitors

1

2

4

† These figures include all four amplifiers and all ESD, bias, and trim circuitry.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

3

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Supply voltage, VCC– (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Input voltage range, VI (any input, see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±80 mA Total current into VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Total current out of VCC– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 mA Duration of short-circuit current at (or below) 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Package thermal impedance, θJA (see Notes 4 and 5): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package (14 pin) . . . . . . . . . . . . . . . . . . . 96°C/W N package (14 pin) . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package (14 pin) . . . . . . . . . . . . . . . . . . . 76°C/W P package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 85°C/W PS package (8 pin) . . . . . . . . . . . . . . . . . . . . 95°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature 1,6 mm (1/16inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–. 2. Differential voltages are at IN+ with respect to IN–. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. 5. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

VCC±

Supply voltage

VIC

Common mode input voltage Common-mode

TA

Operating free-air temperature

4

VCC± = ±5 V VCC± = ±15 V

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

C SUFFIX

I SUFFIX

MIN

MAX

MIN

MAX

±5

±15

±5

±15

–1

4

–1

4

–11

11

–11

11

0

70

–40

85

UNIT V V °C

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL051C and TL051AC electrical characteristics at specified free-air temperature TL051C, TL051AC PARAMETER

TEST CONDITIONS

TL051C VIO

Input offset voltage TL051AC

aV

IO

Temperature coefficient of input offset voltage‡

VO = 0 0, VIC = 0, RS = 50 Ω

IIB

VICR

VOM OM+

25°C

0.75

0.59

4.5

25°C

0.55

Full range

0.8

mV

1.8

8

8

TL051AC

25°C to 70°C

8

8

0.04

0.04

µV/°C

25°C

25 µV/mo

Input offset current

VO = 0, VIC = 0, See Figure 5

25°C

4

100

5

100

pA

70°C

0.02

1

0.025

1

nA

Input bias current

VO = 0, VIC = 0, See Figure 5

25°C

20

200

30

200

pA

70°C

0.15

4

0.2

4

nA

25°C

–1 to 4

Full range

–1 to 4

25°C

3

Full range

3

Common-mode input voltage range

Maximum positive peak output voltage swing

RL = 10 kΩ

25°C

Maximum negative peak g output voltage swing

RL = 10 kΩ

Large-signal L i l differential diff ti l amplification voltage am lification¶

2.5

25°C

–2.5

Full range

–2.5

25°C

–2.3

Full range

–2.3

4.2

V

12.7 –13.2

–11

V

–12

–11

25°C

25

59

50

105

0°C

30

65

60

129

70°C

20

30

85 1012



12

pF

CMRR

Common-mode Common mode rejection ratio

No load

–12

–3.2

10

VO = 0,

13.9

–12

25°C

Supply y current

V

11.5

25°C

RS = 50 Ω

11.5

–3.5

Input capacitance

VO = 0,

13

3.8

Input resistance

Supply voltage rejection Supply-voltage ratio (∆VCC±/∆VIO)

–12.3 to 15.6

13

ci

VIC = VICRmin, min VO = 0 0, RS = 50 Ω

–11 to 11 –11 to 11

2.5

Full range

RL = 2 kΩ

–2.3 to 5.6

ri

ICC

0.35

UNIT

1.5 2.5

2.8 3.8

46 1012

kSVR

3.5

TL051C

RL = 2 kΩ

AVD

VCC± = ±15 V MIN TYP MAX

25°C to 70°C

RL = 2 kΩ

VOM OM–

VCC± = ±5 V MIN TYP MAX

Full range

Input offset-voltage long-term drift§ IIO

TA†

25°C

65

85

75

93

0°C

65

84

75

92

70°C

65

84

75

91

25°C

75

99

75

99

0°C

75

98

75

98

70°C

75

97

75

97

V/mV

dB

dB

25°C

2.6

3.2

2.7

3.2

0°C

2.7

3.2

2.8

3.2

70°C

2.6

3.2

2.7

3.2

mA

† Full range is 0°C to 70°C. ‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

5

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL051C and TL051AC operating characteristics at specified free-air temperature TL051C, TL051AC PARAMETER

SR+

TEST CONDITIONS

Positive P iti slew l rate t at unity gain‡ RL = 2 kΩ,, See Figure 1

SR–

Negative N ti slew l rate t at unity gain‡

tr

Rise time

tf

Fall time

CL = 100 pF,,

VI(PP) = ±10 mV, RL = 2 kΩ, kΩ CL = 100 pF F, See Figures 1 and 2 g

Overshoot factor

25°C

16

13

20

Full range

16.4

11

22.6

25°C

15

13

18

Full range

16

11

19.3

25°C

55

56

0°C

54

55

70°C

63

63

25°C

55

57

0°C

54

56

70°C

62

64

25°C

24

19

0°C

24

19

24

19

25°C

75

75

f = 1 kHz

25°C

18

18

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

25°C

0.003

0.003

25°C

3

3.1

0°C

3.2

3.3

70°C

2.7

2.8

25°C

59

62

0°C

58

62

70°C

59

62

VN(PP)

Peak-to-peak equivalent input noise voltage

In

Equivalent input noise current

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

RL = 2 kΩ,

B1

Unity-gain bandwidth

VI = 10 mV, V CL = 25 pF F,

RL = 2 kΩ, kΩ See Figure 4

VI = 10 mV, mV CL = 25 pF, F,

RL = 2 kΩ, kΩ See Figure 4

Phase margin at unity gain

VCC± = ±15 V MIN TYP MAX

70°C Vn

φm

VCC± = ±5 V MIN TYP MAX

f = 10 Hz

Equivalent input noise q voltage§

RS = 20 Ω, See Figure 3

TA†

UNIT

V/µs

ns

%

30

nV/√Hz µV pA/√Hz %

MHz

deg

† Full range is 0°C to 70°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

6

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL051I and TL051AI electrical characteristics at specified free-air temperature TL051I, TL051AI PARAMETER

TEST CONDITIONS

TL051I VIO

Input offset voltage TL051AI

aV

IO

Temperature coefficient of input offset voltage‡

VO = 0 0, VIC = 0, RS = 50 Ω

IIB

VICR

VOM +

25°C

0.75

0.59

3.5 5.3

25°C

0.55

Full range

0.35

4.6 7

8

TL051AI

25°C to 85°C

8

8

mV

0.04

0.04

µV/°C

25°C

25 µV/mo

Input offset current

VO = 0, VIC = 0, See Figure 5

25°C

4

100

5

100

pA

85°C

0.06

10

0.07

10

nA

Input bias current

VO = 0, VIC = 0, See Figure 5

25°C

20

200

30

200

pA

85°C

0.6

20

0.7

20

nA

25°C

–1 to 4

Full range

–1 to 4

25°C

3

Full range

3

Common-mode input voltage range

Maximum positive peak output voltage swing

RL = 10 kΩ

25°C

Maximum negative g peak output voltage swing

RL = 10 kΩ

Large-signal L i l differential diff ti l amplification voltage am lification¶

RL = 2 kΩ

–2.3 to 5.6

2.5

25°C

–2.5

Full range

–2.5

25°C

–2.3

Full range

–2.3

–12.3 to 15.6

4.2

13

13.9

13 3.8

11.5

V

12.7

11.5 –3.5

–12

–13.2

–12 –3.2

–11

V

–12

–11

25°C

25

59

50

105

–40°C

30

74

60

145

85°C

20

30

76 1012



12

pF

Input resistance

25°C

ci

Input capacitance

25°C

10 65

85

75

93

Common mode Common-mode rejection ratio

VIC = VICRmin, VO = 0, RS = 50 Ω

25°C

CMRR

–40°C

65

83

75

90

85°C

65

84

75

93

25°C

75

99

75

99

Supply-voltage Supply voltage rejection ratio (∆VCC±/∆VIO)

VO = 0, 0 RS = 50 Ω

–40°C

75

98

75

98

85°C

75

99

75

99

Supply current

VO = 0,

No load

V

–11 to 11

2.5

Full range

–11 to 11

ri

ICC

0.8 2.6

43 1012

kSVR

UNIT

1.5 3.3

2.8

TL051I

RL = 2 kΩ

AVD

VCC± = ±15 V MIN TYP MAX

25°C to 85°C

RL = 2 kΩ

VOM –

VCC± = ±5 V MIN TYP MAX

Full range

Input offset-voltage long-term drift§ IIO

TA†

V/mV

dB

dB

25°C

2.6

3.2

2.7

3.2

–40°C

2.4

3.2

2.6

3.2

mA

85°C 2.5 3.2 2.6 3.2 † Full range is –40°C to 85°C ‡ This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC± = ±5 V, VO = ±2.3 V, or for VCC± = ±15 V, VO = ±10 V.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

7

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL051I and TL051AI operating characteristics at specified free-air temperature TL051I, TL051AI PARAMETER

SR+

TEST CONDITIONS

Positive P iti slew l rate t at unity gain‡ RL = 2 kΩ,, See Figure 1

SR–

Negative N ti slew l rate t at unity gain‡

tr

Rise time

tf

Fall time

CL = 100 pF,,

25°C

16

Full range

VI(PP) ( ) = ±10 mV, RL = 2 kΩ, kΩ CL = 100 pF F, See Figures 1 and 2 g

13

UNIT

20

15

13

V/µs

18

11

25°C

55

56

–40°C

52

53

85°C

64

65

25°C

55

57

–40°C

51

53

85°C

64

65

25°C

24

19

–40°C

24

19

ns

%

85°C

24

19

f = 10 Hz

25°C

75

75

f = 1 kHz

25°C

18

18

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

pA/√Hz

25°C

0.003

0.003

%

Vn VN(PP)

Peak-to-peak equivalent input noise voltage

In

Equivalent input noise current

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

RL = 2 kΩ,

B1

Unity-gain bandwidth

VI = 10 mV, V CL = 25 pF F,

RL = 2 kΩ, kΩ See Figure 4

VI = 10 mV, mV CL = 25 pF, F,

RL = 2 kΩ, kΩ See Figure 4

RS = 20 Ω, See Figure 3

VCC± = ±15 V MIN TYP MAX

11

Full range

Equivalent input noise q voltage§

Phase margin at unity gain

VCC± = ±5 V MIN TYP MAX

25°C

Overshoot factor

φm

TA†

25°C

3

3.1

–40°C

3.5

3.6

85°C

2.6

2.7

25°C

59

62

–40°C

58

61

85°C

59

62

30

nV/√Hz µV

MHz

deg

† Full range is –40°C to 85°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL052C and TL052AC electrical characteristics at specified free-air temperature TL052C, TL052AC PARAMETER

TEST CONDITIONS

TL052C VIO

Input offset voltage TL052AC

VO = 0, 0 VIC = 0 0, RS = 50 Ω

aV

IO

IIO IIB

VICR

VOM OM+

Temperature coefficient of input offset voltage‡

0.73

0.65

25°C Full range

2.8

0.4

3.8

6

25°C

0.04

0.04

25°C

4

VIC = 0 0, VIC = 0 0,

µV/°C

5

µV/mo 100

pA

0.02

1

0.025

1

nA

20

200

30

200

pA

70°C

0.15

4

0.2

4

nA

25°C

–1 to 4

Full range

–1 to 4

25°C

3

Full range

3

–2.3 to 5.6

2.5

25°C

–2.5

Full range

–2.5

25°C

–2.3

Full range

–2.3

–11 to 11

–12.3 to 15.6

–11 to 11 4.2

13

3.8

11.5

V

13.9

13

2.5

Full range

RL = 2 kΩ

100

25

70°C

25°C

RL = 10 kΩ

mV

25°C

Common-mode input voltage range

RL = 10 kΩ

0.8 1.8

8

VO = 0,, See Figure 5

Large-signal L i l diff differential ti l voltage am lification¶ amplification

0.51

UNIT

1.5 2.5

25°C to 70°C

Input offset current

Maximum negative g peak output voltage swing

4.5

TL052AC VIC = 0,

Maximum positive peak output voltage swing

3.5

8

RL = 2 kΩ

AVD

25°C Full range

8

RL = 2 kΩ

VOM OM–

VCC± = ±15 V MIN TYP MAX

25°C to 70°C

VO = 0, RS = 50 Ω

VO = 0,, See Figure 5

VCC± = ±5 V MIN TYP MAX

TL052C

Input offset-voltage long-term drift§

Input bias current

TA†

12.7

V

11.5 –3.5

–12

–13.2

–12 –3.2

–11

–12

V

–11

25°C

25

59

50

105

0°C

30

65

60

129

70°C

20

46

30

85

V/mV

ri

Input resistance

25°C

1012

1012



ci

Input capacitance

25°C

10

12

pF

CMRR

Common mode Common-mode rejection ratio

min VIC = VICRmin, VO = 0,

RS = 50 Ω

25°C

65

85

75

93

0°C

65

84

75

92

70°C

65

84

75

91

dB

† Full range is 0°C to 70°C. ‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ For VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

9

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL052C and TL052AC electrical characteristics at specified free-air temperature (continued) TL052C, TL052AC PARAMETER

Supply-voltage S l lt rejection j ti ratio (∆VCC±/∆VIO)

kSVR

S l currentt Supply (two amplifiers) am lifiers)

ICC VO1/VO2

Crosstalk attenuation

TEST CONDITIONS

VO = 0,

VO = 0,

TA

RS = 50 Ω

No load

AVD = 100

VCC± = ±5 V MIN TYP MAX

VCC± = ±15 V MIN TYP MAX

25°C

75

99

75

99

0°C

75

98

75

98

70°C

75

97

75

UNIT

dB

97

25°C

4.6

5.6

4.8

5.6

0°C

4.7

6.4

4.8

6.4

70°C

4.4

6.4

4.6

6.4

25°C

120

mA

120

dB

VCC± = ±15 V MIN TYP MAX

UNIT

TL052C and TL052AC operating characteristics at specified free-air temperature TL052C, TL052AC PARAMETER

SR+

Slew rate at unity gain

SR SR–

Negative g slew rate at unity gain‡

tr

tf

TEST CONDITIONS

RL = 2 kΩ,

CL = 100 pF,

See Figure 1

Equivalent q input noise voltage§

Peak-to-peak equivalent VN(PP) input noise current

VI(PP) ( ) = ±10 mV, RL = 2 kΩ, kΩ CL = 100 pF F, See Figures g 1 and 2

RS = 20 Ω, See Figure 3

20.7

8 15.4

9

V/µs

17.8

8

25°C

55

56

0°C

54

55

70°C

63

63

25°C

55

57

0°C

54

56

70°C

62

64

25°C

24

19

ns

%

0°C

24

19

24

19

f = 10 Hz

25°C

71

71

f = 1 kHz

25°C

19

19

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

pA/√Hz

25°C

0.003

0.003

%

25°C

3

3

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

RL = 2 kΩ,

Unity-gain bandwidth

VI = 10 mV, V CL = 25 pF F,

RL = 2 kΩ, kΩ See Figure 4

mV VI = 10 mV, CL = 25 pF, F,

kΩ RL = 2 kΩ, See Figure 4

φm

9

70°C

Equivalent input noise current

Phase margin at unity gain

17.8

Full range

In

B1

25°C 25°C

Overshoot factor

Vn

VCC± = ±5 V MIN TYP MAX

Full range

Rise time

Fall time

TA†

0°C

3.2

3.2

70°C

2.6

2.7

25°C

60

63

0°C

59

63

70°C

60

63

30

nV/√Hz µV

MHz

deg

† Full range is 0°C to 70°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

10

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL052I and TL052AI electrical characteristics at specified free-air temperature TL052I, TL052AI PARAMETER

TL052I VIO

Input offset voltage TL052AI

VO = 0, 0 VIC = 0, RS = 50 Ω

aV

IO

TA†

TEST CONDITIONS

VCC± = ±5 V MIN TYP MAX

VCC± = ±15 V MIN TYP MAX

0.73

0.65

25°C Full range

3.5 5.3

25°C

0.51

Full range

0.4

4.6

0.8

mV

2.6

TL052I

25°C to 85°C

7

6

TL052AI

25°C to 85°C

6

6

0.04

0.04

T Temperature t coefficient ffi i t‡

1.5 3.3

2.8

UNIT

µV/°C 25

Input offset-voltage long-term drift§

VO = 0, RS = 50 Ω

VIC = 0,

25°C

IIO

Input offset current

VO = 0,, See Figure 5

VIC = 0,,

25°C

4

100

5

100

pA

85°C

0.06

10

0.07

10

nA

IIB

Input bias current

VO = 0,, See Figure 5

VIC = 0,,

25°C

20

200

30

200

pA

85°C

0.6

20

0.7

20

nA

25°C VICR

Common-mode input voltage range Full range

VOM OM+

Maximum positive peak output voltage swing

25°C

RL = 10 kΩ

Full range 25°C

RL = 2 kΩ

VOM OM–

Maximum negative g peak output voltage swing

Full range 25°C

RL = 10 kΩ

Full range 25°C

RL = 2 kΩ

Full range

–11 to 11

3

4.2

3

13

13.9

13

2.5

3.8

2.5

11.5

V

12.7

V

11.5

–2.5

–3.5

–2.5

–12

–13.2

–12

–2.3

–3.2

–2.3

–11

–12

V

–11 50

105

–40°C

30

74

60

145

V/mV

85°C

20

43 1012

30

76 1012



12

pF

Input resistance

25°C

ci

Input capacitance

25°C VIC = VICRmin, min RS = 50 Ω VO = 0,

–12.3 to 15.6

59

ri

Common-mode Common mode rejection ratio

–1 to 4

–11 to 11

25

Large-signal L i l diff differential ti l voltage am lification¶ amplification

CMRR

–2.3 to 5.6

25°C AVD

RL = 2 kΩ

–1 to 4

µV/mo

10

25°C

65

85

75

93

–40°C

65

83

75

90

85°C

65

84

75

93

dB

† Full range is –40°C to 85°C. ‡ This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters § Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. ¶ At VCC± = ±5 V, VO = ±2.3 V; at VCC± = ±15 V, VO = ±10 V.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

11

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL052I and TL052AI electrical characteristics at specified free-air temperature (continued) TL052I, TL052AI PARAMETER

Supply-voltage S l lt rejection j ti ratio (∆VCC±/∆VIO)

kSVR

S l currentt Supply (two amplifiers) am lifiers)

ICC VO1/VO2

Crosstalk attenuation

TEST CONDITIONS

VO = 0,

VO = 0,

TA

RS = 50 Ω

No load

AVD = 100

VCC± = ±5 V MIN TYP MAX

VCC± = ±15 V MIN TYP MAX

25°C

75

99

75

99

–40°C

75

98

75

98

85°C

75

99

75

UNIT

dB

99

25°C

4.6

5.6

4.8

5.6

–40°C

4.5

6.4

4.7

6.4

85°C

4.4

6.4

4.6

6.4

25°C

120

mA

120

dB

VCC± = ±15 V MIN TYP MAX

UNIT

TL052I and TL052AI operating characteristics at specified free-air temperature TL052I, TL052AI PARAMETER

SR+

Sl Slew rate t att unity it gain i ‡

SR SR–

Negative g slew rate at unity gain‡

tr

tf

TA†

TEST CONDITIONS

25°C RL = 2 kΩ,, See Figure 1

CL = 100 pF,,

25°C

Equivalent q input noise voltage§

Peak-to-peak equivalent VN(PP) input noise current

V/µs

17.8

8

–40°C

52

53

85°C

64

65

25°C

55

57

–40°C

51

53

85°C

64

65

25°C

24%

19%

–40°C

24%

19%

85°C

24%

19

f = 10 Hz

25°C

71

71

f = 1 kHz

25°C

19

19

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

pA/√Hz

25°C

0.003

0.003

%

25°C

3

3

–40°C

3.5

3.6

85°C

2.5

2.6

25°C

60

63

–40°C

58

61

85°C

60

63

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

RL = 2 kΩ,

Unity-gain bandwidth

VI = 10 mV, V CL = 25 pF F,

RL = 2 kΩ, kΩ See Figure 4

mV VI = 10 mV, CL = 25 pF, F,

kΩ RL = 2 kΩ, See Figure 4

φm

9

56

Equivalent input noise current

Phase margin at unity gain

15.4 55

In

B1

20.7

25°C

VI(PP) = ±10 mV, RL = 2 kΩ, CL = 100 pF, See Figures 1 and 2

RS = 20 Ω, See Figure 3

9 8

Full range

Overshoot factor

Vn

17.8

Full range

Rise time

Fall time

VCC± = ±5 V MIN TYP MAX

ns

%

30

nV/√Hz µV

MHz

deg

† Full range is –40°C to 85°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

12

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL054C and TL054AC electrical characteristics at specified free-air temperature TL054C, TL054AC PARAMETER

TEST CONDITIONS

TL054C VIO

Input offset voltage TL054AC

aV

IO

Temperature coefficient of input offset voltage

VO = 0 0, VIC = 0, RS = 50 Ω

IIB

VICR

VOM OM+

25°C

0.64

0.56

3.5

0.5

5.7

UNIT

4 6.2 1.5

mV

3.7

25

23

TL054AC

25°C to 70°C

24

23

0.04

0.04

µV/°C

25°C

µV/mo

Input offset current

VO = 0, VIC = 0, See Figure 5

25°C

4

100

5

100

pA

70°C

0.02

1

0.025

1

nA

Input bias current

VO = 0, VIC = 0, See Figure 5

25°C

20

200

30

200

pA

70°C

0.15

4

0.2

4

nA

25°C

–1 to 4

Full range

–1 to 4

25°C

3

Full range

3

Common-mode input voltage range

Maximum positive peak output voltage swing

RL = 10 kΩ

25°C

Maximum negative g peak output voltage swing

RL = 10 kΩ

Large-signal L i l differential diff ti l voltage am lification§ amplification

2.5

25°C

–2.5

Full range

–2.5

25°C

–2.3

Full range

–2.3

RL = 2 kΩ

VCC± = ±5 V to ±15 V, V VO = 0 0, RS = 50 Ω

Supply current am lifiers) (four amplifiers)

VO = 0,

No load

–12.3 to 15.6

V

–11 to 11 4.2

13

13.9

13 3.8

11.5

V

12.7

11.5 –3.5

–12

–13.2

–12 –3.2

–11

V

–12

–11 72

50

133

0°C

30

88

60

173

V/mV

70°C

20

57 1012

30

85 1012



12

pF

25°C

Supply-voltage Supply voltage rejection ratio (∆VCC±/∆VIO)

–11 to 11

25

Input capacitance VIC = VICRmin, min VO = 0 0, RS = 50 Ω

–2.3 to 5.6

25°C

ci

Common-mode Common mode rejection ratio

2.5

Full range

25°C

ICC

0.57

Full range

Input resistance

kSVR

7.7

25°C

ri

CMRR

5.5

TL054C

RL = 2 kΩ

AVD

VCC± = ±15 V MIN TYP MAX

25°C to 70°C

RL = 2 kΩ

VOM OM–

VCC± = ±5 V MIN TYP MAX

Full range

Input offset-voltage long-term drift‡ IIO

TA†

10

25°C

65

84

75

92

0°C

65

84

75

92

70°C

65

84

75

93

25°C

75

99

75

99

0°C

75

99

75

99

70°C

75

99

75

99

dB

dB

25°C

8.1

11.2

8.4

11.2

0°C

8.2

12.8

8.5

12.8

70°C

7.9

11.2

8.2

11.2

mA

VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB † Full range is 0°C to 70°C. ‡ Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. § For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V.B

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

13

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL054C and TL054AC operating characteristics at specified free-air temperature TL054C, TL054C PARAMETER

SR+

SR SR–

tr

tf

TEST CONDITIONS

Positive slew rate at unity gain

Negative g slew rate at unity gain‡

RL = 2 kΩ, CL = 100 pF, See Figure 1 and Note 7

Rise time

Fall time

VI(PP) = ±10 mV, RL = 2 kΩ, kΩ CL = 100 pF F, See Figures 1 and 2

Overshoot factor

25°C

15.4

10

17.8

0°C

15.7

8

17.9

70°C

14.4

8

17.5

25°C

13.9

10

15.9

0°C

14.3

8

16.1

70°C

13.3

8

15.5

25°C

55

56

0°C

54

55

70°C

63

63

25°C

55

57 56

0°C

54

70°C

62

64

25°C

24%

19%

UNIT

V/µs

ns

24%

19%

24%

19

f = 10 Hz

25°C

75

75

f = 1 kHz

25°C

21

21

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

pA/√Hz

25°C

0.003

0.003

%

25°C

2.7

2.7

0°C

3

3

70°C

2.4

2.4

25°C

61

64

0°C

60

64

70°C

61

63

VN(PP)

Peak-to-peak equivalent input noise voltage

In

Equivalent input noise current

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

B1

Unity-gain bandwidth

VI = 10 mV, mV CL = 25 pF F,

RL = 2 kΩ, kΩ See Figure 4

VI = 10 mV, mV CL = 25 pF F,

RL = 2 kΩ kΩ, See Figure 4

Phase margin at unity gain

VCC± = ±15 V MIN TYP MAX

0°C

Equivalent q input noise voltage§

φm

VCC± = ±5 V MIN TYP MAX

70°C Vn

RS = 20 Ω, See Figure 3

TA†

RL = 2 kΩ,

%

45

nV/√Hz µV

MHz

deg

† Full range is 0°C to 70°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

14

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL054I and TL054AI electrical characteristics at specified free-air temperature TL054I, TL054AI PARAMETER

TEST CONDITIONS

TL054I VIO

Input In ut offset voltage TL054AI

aV

IO

Temperature coefficient of input offset voltage

VO = 0 0, VIC = 0, RS = 50 Ω

IIB

VICR

VOM OM+

25°C

0.64

0.56

3.5

0.5

6.8

UNIT

4 7.3 1.5

mV

4.8

25

24

TL054AI

25°C to 85°C

25

23

0.04

0.04

µV/°C

25°C

µV/mo

Input offset current

VO = 0, VIC = 0, See Figure 5

25°C

4

100

5

100

pA

85°C

0.06

10

0.07

10

nA

Input bias current

VO = 0, VIC = 0, See Figure 5

25°C

20

200

30

200

pA

85°C

0.6

20

0.7

20

nA

25°C

–1 to 4

Full range

–1 to 4

25°C

3

Full range

3

Common-mode input voltage range

Maximum positive peak output voltage swing

RL = 10 kΩ

25°C

Maximum negative g peak output voltage swing

RL = 10 kΩ

Large-signal L i l differential diff ti l voltage am lification§ amplification

2.5

Full range

2.5

25°C

–2.5

Full range

–2.5

25°C

–2.3

Full range

–2.3

RL = 2 kΩ

–2.3 to 5.6

–11 to 11

–12.3 to 15.6

V

–11 to 11 4.2

13

13.9

13 3.8

11.5

V

12.7

11.5 –3.5

–12

–13.2

–12 –3.2

–11

V

–12

–11

25°C

25

72

50

133

–40°C

30

101

60

212

V/mV

85°C

20

50 12 10

30

70 12 10



12

pF

25°C

ci

Input capacitance

25°C

ICC

0.57

Full range

Input resistance

kSVR

8.8

25°C

ri

CMRR

5.5

TL054I

RL = 2 kΩ

AVD

VCC± = ±15 V MIN TYP MAX

25°C to 85°C

RL = 2 kΩ

VOM OM–

VCC± = ±5 V MIN TYP MAX

Full range

Input offset voltage long-term drift‡ IIO

TA†

10

25°C

65

84

75

92

Common mode Common-mode rejection ratio

min VIC = VICRmin, VO = 0 0, RS = 50 Ω

–40°C

65

83

75

92

85°C

65

84

75

93

VCC± = ±5 V to ±15 V, V VO = 0 0, RS = 50 Ω

25°C

75

99

75

99

Supply-voltage Supply voltage rejection ratio (∆VCC±/∆VIO)

–40°C

75

98

75

99

85°C

75

99

75

99

25°C

8.1

11.2

8.4

11.2

Supply current am lifiers) (four amplifiers)

VO = 0,

–40°C

7.9

12.8

8.2

12.8

85°C

7.6

11.2

7.9

11.2

No load

dB

dB

mA

VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB † Full range is –40°C to 85°C. ‡ Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV. § For VCC± = ±5 V, VO = ±2.3 V, at VCC± = ±15 V, VO = ±10 V.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

15

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TL054I and TL054AI operating characteristics at specified free-air temperature TL054I, TL054AI PARAMETER

SR+

SR SR–

tr

tf

TEST CONDITIONS

Negative g slew rate at unity gain‡

VCC± = ±15 V MIN TYP MAX

15.4

10

–40°C

16.4

8

18

85°C

14

8

17.3

25°C

13.9

10

15.9

–40°C

14.7

8

16.1

85°C

13

8

15.3

25°C

55

56

–40°C

52

53

85°C

64

65

25°C

55

57

–40°C

51

53

85°C

64

65

25°C

24

19

–40°C

24

19

85°C

24

19

f = 10 Hz

25°C

75

75

f = 1 kHz

25°C

21

21

f = 10 Hz to 10 kHz

25°C

4

4

25°C

0.01

0.01

25°C

0.003%

0.003%

CL = 100 pF,

Rise time

Fall time

VCC± = ±5 V MIN TYP MAX

25°C

Positive slew rate at unity gain RL = 2 kΩ, See Figure 1

TA†

VI(PP) = ±10 mV, RL = 2 kΩ, CL = 100 pF, See Figures 1 and 2

Overshoot factor

17.8

Vn

Equivalent q input noise voltage§

VN(PP)

Peak-to-peak equivalent input noise voltage

In

Equivalent input noise current

f = 1 kHz

THD

Total harmonic distortion¶

RS = 1 kΩ, f = 1 kHz

25°C

2.7

2.7

B1

Unity-gain bandwidth

mV VI = 10 mV, CL = 25 pF F,

kΩ RL = 2 kΩ, See Figure 4

–40°C

3.3

3.3

85°C

2.3

2.4

VI = 10 mV, mV CL = 25 pF F,

RL = 2 kΩ kΩ, See Figure 4

25°C

61

64

–40°C

59

62

85°C

61

64

φm

Phase margin at unity gain

RS = 20 Ω, See Figure 3

RL = 2 kΩ,

UNIT

V/µs

ns

%

45

nV/√Hz µV pA/√Hz %

MHz

deg

† Full range is –40°C to 85°C. ‡ For VCC± = ±5 V, VI(PP) = ±1 V; for VCC± = ±15 V, VI(PP) = ±5 V. § This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. ¶ For VCC± = ±5 V, VO(RMS) = 1 V; for VCC± = ±15 V, VO(RMS) = 6 V.

16

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

PARAMETER MEASUREMENT INFORMATION VCC+ Overshoot

– VO

+

VI

VCC– CL (see Note A)

90%

RL 10% tr

NOTE A: CL includes fixture capacitance.

Figure 1. Slew Rate, Rise/Fall Time, and Overshoot Test Circuit

Figure 2. Rise-Time and Overshoot Waveform

2 kΩ

10 kΩ VCC+ VO

100 Ω

VO

VCC–

– + VCC– RS



VI

+

VCC+

CL (see Note A)

RS

RL

NOTE A: CL includes fixture capacitance.

Figure 3. Noise-Voltage Test Circuit

Figure 4. Unity-Gain Bandwidth and Phase-Margin Test Circuit

typical values

Ground Shield

VCC+ + –

Typical values, as presented in this data sheet represent the median (50% point) of device parametric performance. pA

pA

VCC–

input bias and offset current At the picoamp-bias-current level typical of the TL05x and TL05xA, accurate measurement of the Figure 5. Input-Bias and Offset-Current Test Circuit bias current becomes difficult. Not only does this measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied, but with no device in the socket. The device then is inserted in the socket, and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements then are subtracted algebraically to determine the bias current of the device.

noise Because of the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density is sample tested at f = 1 kHz. Texas Instruments also has additional noise-testing capability to meet specific application requirements. Please contact the factory for details.

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17

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO

Input offset voltage

Distribution

6–11

aV

Temperature coefficient of input offset voltage

Distribution

12, 13, 14

IIB

Input bias current

vs Common-mode input voltage vs Free-air temperature

15 16

IIO

Input offset current

vs Free-air temperature

16

VIC

Common-mode input voltage range limits

vs Supply voltage vs Free-air temperature

17 18

VO

Output voltage

vs Differential input voltage

19, 20

VOM

Maximum peak output voltage

vs Supply voltage vs Output current vs Free-air temperature

21 25, 26 27, 28

VO(PP)

Maximum peak-to-peak output voltage

vs Frequency

22, 23, 24

AVD

Large-signal differential voltage amplification

vs Load resistance vs Frequency vs Free-air temperature

29 30 31, 32, 33

CMRR

Common-mode rejection ratio

vs Frequency vs Free-air temperature

34, 35 36

zo

Output impedance

vs Frequency

37

kSVR

Supply-voltage rejection ratio

vs Free-air temperature

38

IOS

Short-circuit output current

vs Supply voltage vs Time vs Free-air temperature

39 40 41

ICC

Supply current

vs Supply voltage vs Free-air temperature

42, 43, 44 45, 46, 47

SR

Slew rate

vs Load resistance vs Free-air temperature

48–53 54–59

Overshoot factor

vs Load capacitance

Equivalent input noise voltage

vs Frequency

Total harmonic distortion

vs Frequency

B1

Unity-gain bandwidth

vs Supply voltage vs Free-air temperature

64, 65, 66 67, 68, 69

φm

Phase margin

vs Supply voltage vs Load capacitance vs Free-air temperature

70, 71, 72 73, 74, 75 76, 77, 78

Phase shift

vs Frequency

30

Voltage-follower small-signal pulse response

vs Time

79

Voltage-follower large-signal pulse response

vs Time

80

IO

Vn THD

18

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60 61, 62 63

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS DISTRIBUTION OF TL051A INPUT OFFSET VOLTAGE

DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE

12

20 433 Units Tested From 1 Wafer Lot VCC± = ±15 V TA = 25°C P Package

16 Percentage of Units – %

Percentage of Units – %

16

8

4

ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 393 Units Tested From 1 Wafer Lot VCC± = ±15 V TA = 25°C P Package

12

8

4

0 –1.5 –1.1 –0.9 –0.6 –0.3

0

0.3

0 –900

0.9 1.1 1.5

0.6

–600

300

600

900

Figure 7

Figure 6 DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE

DISTRIBUTION OF TL052A INPUT OFFSET VOLTAGE 20

15 476 Amplifiers Tested From 1 Wafer Lot VCC± = ±15 V TA = 25°C P Package

Percentage of Amplifiers – %

Percentage of Amplifiers – %

0

VIO – Input Offset Voltage – µV

VIO – Input Offset Voltage – mV

12

–300

9

6

15

403 Amplifiers Tested From 1 Wafer Lot VCC± = ±15 V TA = 25°C P Package

10

5

3

0 –1.5 –1.2 –0.9 –0.6 –0.3

0

0.3

0.6

0.9

1.2 1.5

0 –900

–600

–300

0

300

600

900

VIO – Input Offset Voltage – µV

VIO – Input Offset Voltage – mV

Figure 8

Figure 9

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS DISTRIBUTION OF TL054A INPUT OFFSET VOLTAGE

DISTRIBUTION OF TL054 INPUT OFFSET VOLTAGE 30

15

Percentage of Amplifiers – %

25

Percentage of Amplifiers – %

1140 Amplifiers Tested From 3 Wafer Lots VCC± = ±15 V TA = 25°C N Package

20

15

10

5

0 –4

–3

–2

–1

0

1

2

3

12

1048 Amplifiers Tested From 3 Wafer Lots VCC± = ±15 V TA = 25°C N Package

9

6

3

0 –1.8

4

–1.2

–0.6

Percentage of Amplifiers – %

Percentage of Units – %

ÎÎÎÎÎÎÎÎÎÎ

12

8

4

aV

IO

5

10

15

ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ

20

120 Units Tested From 2 Wafer Lots VCC± = ±15 V TA = 25°C to 125°C P Package

0

20

25

– Temperature Coefficient – µV/°C

15

172 Amplifiers Tested From 2 Wafer Lots VCC± = ±15 V TA = 25°C to 125°C P Package Outlier: One Unit at –34.6 µV/°C

10

5

0 –30

–20

–10

0

IO

Figure 13

POST OFFICE BOX 655303

10

20

a V – Temperature Coefficient – µV/°C

Figure 12

20

1.8

DISTRIBUTION OF TL052 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT

DISTRIBUTION OF TL051 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT

0 –25 –20 –15 –10 –5

1.2

Figure 11

Figure 10

16

0.6

VIO – Input Offset Voltage – mV

VIO – Input Offset Voltage – mV

20

0

• DALLAS, TEXAS 75265

30

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE

DISTRIBUTION OF TL054 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT

ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 324 Amplifiers Tested From 3 Wafer Lots VCC± = ±15 V TA = 25°C to 125°C N Package

Percentage of Amplifiers – %

40

30

20

10 VCC± = ±15 V TA = 25°C IB – Input Bias Current – nA

50

I

10

0 –60

–40

aV

–20

IO

0

20

40

5

0

–5

–10 –15

60

– Temperature Coefficient – µV/°C

–10

Figure 14

0

5

10

15

Figure 15

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT† vs FREE-AIR TEMPERATURE

COMMON-MODE INPUT VOLTAGE RANGE LIMITS vs SUPPLY VOLTAGE 16

100

VCC± = ±15 V VO = 0 VIC = 0

TA = 25°C VIC – Common-Mode Input Voltage – V

I

IB and IO – Input Bias and Offset Currents – nA

–5

VIC – Common-Mode Input Voltage – V

10 IIB 1 IIO 0.1

0.01

12

ÎÎÎÎÎ

8

Positive Limit

4

ÎÎÎÎÎ

0

Negative Limit

–4 –8 –12

I 0.001

–16 25

45 65 85 105 TA – Free-Air Temperature – °C

125

0

2

4 6 8 10 12 |VCC±| – Supply Voltage – V

14

16

Figure 17

Figure 16

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE RANGE LIMITS† vs FREE-AIR TEMPERATURE

20

OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE

ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ

ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

5

15

Positive Limit

10

3

5 0

ÎÎÎÎÎ ÎÎÎÎÎ

–5

Negative Limit

–10 –15 –20 –75

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

VCC± = ±5 V TA = 25°C

4

VO – Output Voltage – V

VIC – Common-Mode Input Voltage – V

VCC± = ±15 V

2 1

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

0

RL = 600 Ω RL = 1 kΩ

–1 –2

–5 –200

125

–100

16 VOM+

TA = 25°C VOM – Maximum Peak Output Voltage – V

VO – Output Voltage – V

200

MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE

VCC± = ±15 V TA = 25°C

5

ÁÁÁÁ ÁÁÁÁ ÎÎÎÎ ÁÁÁÁ ÎÎÎÎ ÁÁÁÁ ÎÎÎÎ

0

RL = 600 Ω RL = 1 kΩ RL = 2 kΩ RL = 10 kΩ

–5

–10

–200

100

Figure 19

ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ

–15 –400

0

VID – Differential Input Voltage – µV

OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE

10

RL = 2 kΩ RL = 10 kΩ

–4

Figure 18

15

ÎÎÎÎÎ ÎÎÎÎÎ

–3

0

200

400

12 RL = 10 kΩ 8 RL = 2 kΩ 4 0 –4 RL = 2 kΩ –8 RL = 10 kΩ –12 VOM– –16 0

2

VID – Differential Input Voltage – µV

Figure 20

4 6 8 10 12 |VCC±| – Supply Voltage – V

14

Figure 21

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

22

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS

30 RL = 2 kΩ

VCC± = ±15 V 25

20

15 TA = 125°C 10

TA = –55°C

VCC± = ±5 V

5

0 10 k

100 k 1M f – Frequency – Hz

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY VO(PP) – Maximum Peak-to-Peak Output Voltage – V

VO(PP) – Maximum Peak-to-Peak Output Voltage – V

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE† vs FREQUENCY

10 M

30

25

ÁÁÁÁÁ ÁÁÁÁÁ

15

10

5

ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±5 V

0 10 k

100 k

15

ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±5 V

5

0 10 k

100 k

1M

10 M

MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

5 |VOM| – Maximum Peak Output Voltage – V

VO(PP) – Maximum Peak-to-Peak Output Voltage – V

ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±15 V

10

10 M

Figure 23

RL = 10 kΩ TA = 25°C

20

1M

f – Frequency – Hz

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY

25

RL = 2 kΩ TA = 25°C

20

Figure 22

30

ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ

VCC± = ±15 V

VCC± = ±5 V RL = 10 kΩ TA = 25°C

4

3

ÁÁÁ ÁÁÁ

2

VOM–

1

ÁÁÁ ÁÁÁ VOM+

0 0

2

f – Frequency – Hz

4

6

8

10

12

14

16

18

20

|IO| – Output Current – mA

Figure 24

Figure 25

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS MAXIMUM PEAK OUTPUT VOLTAGE† vs FREE-AIR TEMPERATURE

MAXIMUM PEAK OUTPUT VOLTAGE vs OUTPUT CURRENT

|VOM| – Maximum Peak Output Voltage – V

VCC± = ±15 V RL = 10 kΩ TA = 25°C

14 12

VOM+

10 8

VOM–

6 4 2

5

5

10

15 20 25 30 35 40 |IO| – Output Current – mA

45

4 RL = 2 kΩ

3 2 1

VCC± = ±5 V

0 –1 –2 –3

ÁÁÁ ÁÁÁ VOM–

50

RL = 10 kΩ –50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

Figure 26

LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE

ÁÁÁ ÁÁÁ VOM+

8

250

RL = 10 kΩ

A VD – Differential Voltage Amplification – V/mV

V OM – Maximum Peak Output Voltage – V

12

RL = 2 kΩ

4 VCC± = ±15 V 0 –4 –8 –12

ÁÁÁ ÁÁÁ

–16 –75

VOM–

RL = 2 kΩ RL = 10 kΩ

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

125

VO = ±1 V TA = 25°C

200

VCC± = ±15 V

150 VCC± = ±5 V 100

50

0 0.4

1

4 10 RL – Load Resistance – kΩ

40

Figure 29

Figure 28

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

24

125

Figure 27

MAXIMUM PEAK OUTPUT VOLTAGE† vs FREE-AIR TEMPERATURE 16

RL = 2 kΩ

–4 –5 –75

0 0

RL = 10 kΩ

VOM+ V OM – Maximum Peak Output Voltage – V

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ

16

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100

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY VCC± = ±15 V RL = 2 kΩ CL = 25 pF TA = 25°C

105 104

0° 30°

AVD 103

φ m – Phase Shift

A VD – Differential Voltage Amplification – V/mV

106

60° 90°

102

Phase Shift

101

120°

1

150°

0.1 10

100

1k 10 k 100 k f – Frequency – Hz

1M

180° 10 M

Figure 30 TL054 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION† vs FREE-AIR TEMPERATURE

TL051 AND TL052 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION† vs FREE-AIR TEMPERATURE 1000 A VD – Differential Voltage Amplification – V/mV

A VD – Differential Voltage Amplification – V/mV

1000 VCC± = ±5 V VO = ±2.3 V 400

RL = 10 kΩ 100

RL = 2 kΩ

40

10 –75

–50

–25

0

25

50

75

100

125

VCC± = ±5 V VO = ±2.3 V 400

RL = 10 kΩ 100 RL = 2 kΩ 40

10 –75

–50

–25

0

25

50

75

100

125

TA – Free-Air Temperature – °C

TA – Free-Air Temperature – °C

Figure 32

Figure 31

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION† vs FREE-AIR TEMPERATURE

ÁÁÁÁÁ ÁÁÁÁÁ VCC± = ±15 V VO = 10 V

RL = 10 kΩ

400

100

RL = 2 kΩ

40

10 –75

100 CMRR – Common-Mode Rejection Ratio – dB

A VD – Differential Voltage Amplification – V/mV

1000

COMMON-MODE REJECTION RATIO vs FREQUENCY VCC± = ±5 V TA = 25°C

90 80 70 60 50 40 30 20 10 0

–50

–25

0

25

50

75

125

100

10

100

TA – Free-Air Temperature – °C

Figure 33

10 k

100 k

1M

10 M

Figure 34 COMMON-MODE REJECTION RATIO† vs FREE-AIR TEMPERATURE

COMMON-MODE REJECTION RATIO vs FREQUENCY 100 VCC± = ±15 V TA = 25°C

90 80 70 60 50 40 30 20 10 0 10

100

1k

10 k

100 k

1M

10 M

CMRR – Common-Mode Rejection Ratio – dB

100 CMRR – Common-Mode Rejection Ratio – dB

1k

f – Frequency – Hz

VIC = VICRMin 95

VCC± = ±15 V

90

85 VCC± = ±5 V 80

75

70 –75

–50

–25

0

25

50

75

100

125

TA – Free-Air Temperature – °C

f – Frequency – Hz

Figure 35

Figure 36

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

26

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS SUPPLY-VOLTAGE REJECTION RATIO† vs FREE-AIR TEMPERATURE

OUTPUT IMPEDANCE vs FREQUENCY 110 AVD = 100

40 zo – Output Impedance – Ω

kkSVR SVR – Supply-Voltage Rejection Ratio – dB

100

10 AVD = 10 4

1 AVD = 1 0.4

VCC± = ±15 V TA = 25°C ro (open loop) ≈ 250 Ω

0.1 1k

10 k 100 k f – Frequency – Hz

1M

ÁÁ ÁÁ ÁÁ

VCC± = ±5 V to ±15 V 106

102

98

94

90 –75

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

Figure 37

Figure 38 SHORT-CIRCUIT OUTPUT CURRENT vs TIME

SHORT-CIRCUIT OUTPUT CURRENT vs SUPPLY VOLTAGE 60 VO = 0 TA = 25°C

40

IIOS OS – Short-Circuit Output Current – mA

IOS I OS – Short-Circuit Output Current – mA

60

VID = 100 mV 20

0

–20

ÁÁ ÁÁ

125

VID = –100 mV

–40

–60 0

2

4

6 8 10 12 |VCC±| – Supply Voltage – V

14

16

ÁÁ ÁÁ ÁÁ

VID = 100 mV 40

20

–20

–40 VID = –100 mV –60

VCC± = ±15 V TA = 25°C

0 0

10

Figure 39

20 30 t – Time – s

40

50

60

Figure 40

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL051 SUPPLY CURRENT† vs SUPPLY VOLTAGE

SHORT-CIRCUIT OUTPUT CURRENT† vs FREE-AIR TEMPERATURE 3 VCC± = ±15 V

ÎÎÎÎÎ ÎÎÎÎÎ

40

2.5

VID = 100 m V

20

IICC CC – Supply Current – mA

IIOS OS – Short-Circuit Output Current – mA

60

VCC± = ±5 V

0

ÎÎÎÎÎÎ

–20

ÁÁ ÁÁ

VCC± = ±5 V

VCC± = ±15 V

TA = 125°C 1.5

1

0.5

–40 VO = 0

–60 –75

2

ÁÁ ÁÁ ÁÁ

VID = –100 m V

TA = 25°C TA = –55°C

VO = 0 No Load 0

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

0

125

2

4

TL052 SUPPLY CURRENT† vs SUPPLY VOLTAGE

10

12

14

10

4

8 IICC CC – Supply Current – mA

TA = 25°C TA = –55°C TA = 125°C

3

2

ÁÁ ÁÁ

1 VO = 0 No Load 0

ÎÎÎÎÎ ÎÎÎÎÎ

TA = 25°C TA = –55°C TA = 125°C

6

4

2 VO = 0 No Load 0

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

|VCC±| – Supply Voltage – V

|VCC±| – Supply Voltage – V

Figure 44

Figure 43

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

28

16

TL054 SUPPLY CURRENT† vs SUPPLY VOLTAGE

5

IICC CC – Supply Current – mA

8

Figure 42

Figure 41

ÁÁ ÁÁ ÁÁ

6

|VCC±| – Supply Voltage – V

POST OFFICE BOX 655303

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL052 SUPPLY CURRENT† vs FREE-AIR TEMPERATURE

TL051 SUPPLY CURRENT† vs FREE-AIR TEMPERATURE 5

3

4 IICC CC – Supply Current – mA

IICC CC – Supply Current – mA

2.5 VCC± = ±15 V 2

VCC± = ±5 V

1.5

ÁÁ ÁÁ

1

0.5 VO = 0 No Load

ÁÁ ÁÁ ÁÁ

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

VCC± = ±5 V 3

2

1 VO = 0 No Load 0 –75

0 –75

VCC± = ±15 V

125

–50

–25

25

125

ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ

25 SR+ 20

VCC± = ±5 V

6

SR – Slew Rate – V/µs

IICC CC – Supply Current – mA

100

TL051 SLEW RATE vs LOAD RESISTANCE

VCC± = ±15 V

ÁÁ ÁÁ ÁÁ

75

Figure 46

TL054 SUPPLY CURRENT† vs FREE-AIR TEMPERATURE

8

50

TA – Free-Air Temperature – °C

Figure 45

10

0

4

SR– 15

10

VCC± = ±5 V CL = 100 pF TA = 25°C See Figure 1

5

2 VO = 0 No Load 0 –75

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

125

0 0.4

1

4

10

40

100

RL – Load Resistance – kΩ

Figure 48

Figure 47

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL052 SLEW RATE vs LOAD RESISTANCE

TL054 SLEW RATE vs LOAD RESISTANCE

25

25

ÎÎ

SR+

SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

SR+

20

20

SR–

15

10

15

10

VCC± = ±5 V CL = 100 pF TA = 25°C See Figure 1

5

1

4

40

10

VCC± = ±5 V CL = 100 pF TA = 25°C See Figure 1

5

0 0.4

0 0.4

SR–

100

1

4

25

30

SR+

SR+ 25

20 SR–

SR–

20

15

10 VCC± = ±15 V CL = 100 pF TA = 25°C See Figure 1

5

1

4

10

40

100

SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

100

TL052 SLEW RATE vs LOAD RESISTANCE

TL051 SLEW RATE vs LOAD RESISTANCE

15

10

VCC± = ±15 V CL = 100 pF TA = 25°C See Figure 1

5

0 0.4

1

RL – Load Resistance – kΩ

Figure 51

30

40

Figure 50

Figure 49

0 0.4

10

RL – Load Resistance – kΩ

RL – Load Resistance – kΩ

4 10 RL – Load Resistance – kΩ

Figure 52

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40

100

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL054 SLEW RATE vs LOAD RESISTANCE

TL051 SLEW RATE† vs FREE-AIR TEMPERATURE

25

30 SR+

25

SR– 15

10 VCC± = ±5 V CL = 100 pF TA = 25°C See Figure 1

5

0 0.4

1

4

10

40

SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

20

SR+ 20

SR–

15

10 VCC± = ±5 V RL = 2 kΩ

5

0 –75

100

–50

–25

Figure 53

50

75

100

125

TL054 SLEW RATE† vs FREE-AIR TEMPERATURE 20

25

SR+

20

SR+

15

15 SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

25

Figure 54

TL052 SLEW RATE† vs FREE-AIR TEMPERATURE

SR–

10 VCC± = ±5 V RL = 2 kΩ CL = 100 pF See Figure 1

5

0 –75

0

TA – Free-Air Temperature – °C

RL – Load Resistance – kΩ

–50

–25

0

25

50

75

100

SR–

10

VCC± = ±5 V RL = 2 kΩ CL = 100 pF See Figure 1

5

125

0 –75

–50

TA – Free-Air Temperature – °C

–25

0

25

50

75

100

125

TA – Free-Air Temperature – °C

Figure 56

Figure 55

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL051 SLEW RATE† vs FREE-AIR TEMPERATURE

TL052 SLEW RATE† vs FREE-AIR TEMPERATURE

30

25 SR+

SR+

25

SR – Slew Rate – V/µs

SR – Slew Rate – V/µs

20 20 SR– 15

10 VCC± = ±15 V RL = 2 kΩ CL = 100 pF See Figure 1

5

0 –75

–50

–25

0

25

50

75

100

SR– 15

10 VCC± = ±15 V RL = 2 kΩ CL = 100 pF See Figure 1

5

0 –75

125

–50

TA – Free-Air Temperature – °C

–25

0

25

50

75

100

125

TA – Free-Air Temperature – °C

Figure 57

Figure 58

TL054 SLEW RATE† vs FREE-AIR TEMPERATURE

OVERSHOOT FACTOR vs LOAD CAPACITANCE 50

20 SR+ SR– Overshoot Factor – %

SR – Slew Rate – V/µs

10

5

0 –75

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ

40

15

VCC± = ±15 V RL = 2 kΩ CL = 100 pF See Figure 1

VCC± = ±5 V

30

VCC± = ±15 V

20

VI(PP) = ±10 mV RL = 2 kΩ TA = 25°C See Figure 1

10

0 –50

–25

0

25

50

75

100

125

0

50

TA – Free-Air Temperature – °C

100

150

200

250

CL – Load Capacitance – pF

Figure 59

Figure 60

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

32

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL052 AND TL054 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY

TL051 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY VCC± = ±15 V RS = 20 Ω TA = 25°C See Figure 3

70

50 40 30

20

Vn – Equivalent Input Noise Voltage – nV/ Hz

Vn – Equivalent Input Noise Voltage – nV/ Hz

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

100

100

VCC± = ±15 V RS = 20 Ω TA = 25°C See Figure 3

70

50 40 30

20

10

10 10

100

1k 10 k f – Frequency – Hz

10

100 k

100

Figure 61

TL051 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE 3.2

VCC± = ±15 V AVD = 1 VO(RMS) = 6 V TA = 25°C

B1 – Unity-Gain Bandwidth – MHz

THD – Total Harmonic Distortion – %

1

0.1 0.04

0.01 0.004

0.001 100

1k

100 k

10 k

Figure 62

TOTAL HARMONIC DISTORTION vs FREQUENCY

0.4

1k f – Frequency – Hz

10 k

100 k

f – Frequency – Hz

3.1

3

2.9 VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

2.8

2.7 0

2

4

6

8

10

12

14

16

|VCC±| – Supply Voltage – V

Figure 64

Figure 63

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL054 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE

3.2

2.9

3.1

2.8

B1 – Unity-Gain Bandwidth – MHz

B1 – Unity-Gain Bandwidth – MHz

TL052 UNITY-GAIN BANDWIDTH vs SUPPLY VOLTAGE

3

2.9

ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

2.8

2.7 4

6

8

10

12

14

2.7

ÎÎÎÎ ÁÁÁÁÁ ÁÁÁÁÁ ÎÎÎÎ ÎÎÎÎÎ ÁÁÁÁÁ ÎÎÎÎÎÎ ÎÎÎÎÎ ÁÁÁÁÁ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁ ÎÎÎÎÎÎÎ

2.6

VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

2.5

2.4 0

16

4

2

6

8

12

10

|VCC±| – Supply Voltage – V

|VCC±| – Supply Voltage – V

Figure 65

Figure 66

TL051 UNITY-GAIN BANDWIDTH† vs FREE-AIR TEMPERATURE

14

16

TL052 UNITY-GAIN BANDWIDTH† vs FREE-AIR TEMPERATURE 4

4

B1 – Unity-Gain Bandwidth – MHz

B1 – Unity-Gain Bandwidth – MHz

VCC± = ±15 V 3 VCC± = ±5 V 2

1

0 –75

VI = 10 mV RL = 2 kΩ CL = 25 pF See Figure 4

–50

–25

0

25

50

75

100

125

3

2

1

0 –75

VCC± = ±5 V to ±15 V VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

–50

TA – Free-Air Temperature – °C

–25

0

25

50

75

100

TA – Free-Air Temperature – °C

Figure 68

Figure 67

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

34

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL051 PHASE MARGIN vs SUPPLY VOLTAGE

TL054 UNITY-GAIN BANDWIDTH† vs FREE-AIR TEMPERATURE 65°

63° 3 φ m – Phase Margin

B1 – Unity-Gain Bandwidth – MHz

4

2 VCC± = ±5 V to ±15 V VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

1

0 –75

61°

59° VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

57°

55° –50

–25

0

25

50

75

100

0

125

2

4

TA – Free-Air Temperature – °C

6

Figure 69

65°

65°

63°

63°

61°

59° VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

59°

8

10

16

12

14

16

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4

55° 6

14

61°

57°

55° 4

12

TL054 PHASE MARGIN vs SUPPLY VOLTAGE

φ m – Phase Margin

φ m – Phase Margin

10

Figure 70

TL052 PHASE MARGIN vs SUPPLY VOLTAGE

57°

8

|VCC±| – Supply Voltage – V

0

2

|VCC±| – Supply Voltage – V

4

6

8

10

12

14

16

|VCC±| – Supply Voltage – V

Figure 71

Figure 72

† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL051 PHASE MARGIN† vs LOAD CAPACITANCE

TL052 PHASE MARGIN† vs LOAD CAPACITANCE 70°

70° VI = 10 mV RL = 2 kΩ TA = 25°C See Figure 4

65°

60°

φ m – Phase Margin

φ m – Phase Margin

65°

VI = 10 mV RL = 2 kΩ TA = 25°C See Figure 4

VCC± = ±15 V See Note A 55° VCC± = ±5 V 50°

ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V

60°

See Note A

VCC± = ±5 V

55°

50°

45°

40° 0

10

20 30 40 50 60 70 80 CL – Load Capacitance – pF

45°

90 100

0

10

20 30 40 50 60 70 80 CL – Load Capacitance – pF

Figure 74

Figure 73 TL054 PHASE MARGIN† vs LOAD CAPACITANCE 70° VI = 10 mV RL = 2 kΩ TA = 25°C See Figure 4

φ m – Phase Margin

65°

ÎÎÎÎÎ ÎÎÎÎÎ VCC± = ±15 V

60° See Note A

ÎÎÎÎÎ VCC± = ±5 V

55°

50°

45°

0

10

20 30 40 50 60 70 80 CL – Load Capacitance – pF

Figure 75

† Values of phase margin below a load capacitance of 25 pF were estimated.

36

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90 100

90 100

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS TL052 PHASE MARGIN† vs FREE-AIR TEMPERATURE

TL051 PHASE MARGIN† vs FREE-AIR TEMPERATURE

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

φ m – Phase Margin

63°

65°

VI = 10 mV RL = 2 kΩ CL = 25 pF See Figure 4

63°

VCC± = ±15 V φ m – Phase Margin

65°

61° VCC± = ±5 V 59°

VI = 10 mV RL = 2 kΩ CL = 25 pF See Figure 4

VCC± = ±15 V

61°

59° VCC± = ±5 V 57°

57°

55° –75

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

55°

125

–75

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

125

Figure 77

Figure 76 TL054 PHASE MARGIN† vs FREE-AIR TEMPERATURE 65°

φ m– Phase Margin

63°

VCC± = ±15 V

61°

59°

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

VCC± = ±5 V

VI = 10 mV RL = 2 kΩ CL = 25 pF See Figure 4

57°

55°

–75

–50

–25 0 25 50 75 100 TA – Free-Air Temperature – °C

125

Figure 78 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE

16

8

12

6

8

4 VO – Output Voltage – V

VO – Output Voltage – mV

VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

4

VCC± = ±15 V RL = 2 kΩ CL = 100 pF TA = 25°C See Figure 1

0 –4 –8 –12

VCC± = ±15 V RL = 2 kΩ CL = 100 pF TA = 25°C See Figure 1

0 –2 –4 –6

–16 0

0.2

0.4

0.6

0.8

1.0

1.2

–8 0

t – Time – µs

1

2

3

t – Time – µs

Figure 79

38

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

2

Figure 80

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4

5

6

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION output characteristics All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance. The TL05x and TL05xA drive higher capacitive loads; however, as the load capacitance increases, the resulting response pole occurs at lower frequencies, causing ringing, peaking, or even oscillation. The value of the load capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the problem. Capacitive loads of 1000 pF, and larger, may be driven if enough resistance is added in series with the output (see Figure 81 and Figure 82).

(a) CL = 100 pF, R = 0

(b) CL = 300 pF, R = 0

(c) CL = 350 pF, R = 0

(e) CL = 1000 pF, R = 50 Ω

(d) CL = 1000 pF, R = 0

(f) CL = 1000 pF, R = 2 kΩ

Figure 81. Effect of Capacitive Loads 15 V –

R

VO

+

5V –5 V

–15 V CL (see Note A)

2 kΩ

NOTE A: CL includes fixture capacitance.

Figure 82. Test Circuit for Output Characteristics

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION input characteristics The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets easily can exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 83). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input. Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation. + VI

VO

VO

+ VI

(a) NONINVERTING AMPLIFIER

(b) INVERTING AMPLIFIER

+

VO







VI

(c) UNITY-GAIN AMPLIFIER

Figure 83. Use of Guard Rings

noise performance The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input-bias current requirements of the TL05x and TL05xA result in a very low current noise. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ.

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APPLICATION INFORMATION phase meter The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two input signals VA and VB. The reference signal VA must be the same frequency as VB. The TLC3702 comparators (U1) convert these two input sine waves into ±5-V square waves. Then, R1 and R4 provide level shifting prior to the SN74HC109 dual J-K flip flops. Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of VB. Flip-flop U2A also produces a square wave at one-half the input frequency. The pulse duration of U2A varies from zero to one-half the period, where zero corresponds to zero phase delay between VA and VB and one-half the period corresponds to VB lagging VA by 360 degrees. The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1 and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the 0- to 2.5-V integrator output to a 0- to 3.6-V output range. R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz frequency range. +5 V

R2 100 kΩ

VA U1A

R1 100 kΩ

C2 0.016 µF

+5 V

S 1J U2A C1 1K R

R7

R6 U3 NC

10 kΩ R5 10 kΩ

10 kΩ C1 0.016 µF

+ U4A –

+ U4B –

VO

R9 20 kΩ R3 100 kΩ

S 2J

R8 50 kΩ

NC U2B

C1 R4 100 kΩ

Gain

2K R

+5 V R10 10 kΩ Zero

VB U1B

–5 V

NOTE A: U1 = TLC3702; VCC± = ±5 V U2 = SN74HC109 U3 = TLC4066 U4, U5 = TL05x; VCC± = ±5 V

Figure 84. Phase Meter

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION precision constant-current source over temperature A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R; therefore, the current to the load simply is 2.5 V divided by R. Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator’s cathode connects to the operational amplifier output, this circuit sources load current. Similarly, if the cathode connects to the inverting input, the circuit sinks current from the load. To minimize output current change with temperature, R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with split-voltage supplies. 150 pF

150 pF

U2

U2

+15 V

+15 V 100 kΩ





100 kΩ

U1

U1

+ Load V = 0 to 10 V

+

IO

II

–15 V

Load V = 0 to –10 V

R

(a) SOURCE CURRENT LOAD

2.5 V , R = Low-temperature-coefficient metal-film resistor R

Figure 85. Precision Constant-Current Source

42

POST OFFICE BOX 655303

R

(b) SINK CURRENT LOAD

NOTE A: U1 = 1/2 TL05x U2 = LM385, LT1004, or LT1009 voltage reference I=

–15 V

• DALLAS, TEXAS 75265

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION instrumentation amplifier with adjustable gain/null The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 kΩ, the circuit gain equals 100, while with R1 = 200 kΩ, the circuit gain equals two. The following equation shows the instrumentation amplifier gain as a function of R1: R2 R3 1 AV R1

+ )

ǒ

Ǔ

)

Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5, R6, and R7 controls the CMRR of this application. The following equation shows the output voltages when the input voltage equals zero. This dc error can be nulled by adjusting the offset null potentiometer; however, any change in offset voltage over time or temperature also creates an error. To calculate the error from changes in offset, consider the three offset components in the equation as delta offsets, rather than initial offsets. The improved stability of Texas Instruments enhanced JFETs minimizes the error resulting from change in input offset voltage with time. Assuming VI equals zero, VO can be shown as a function of the offset voltage: V

O

ƪǒ Ǔ ǒ ) Ǔ ǒ ) Ǔ ) ǒ Ǔ ƫ ƪ ǒ ) Ǔ ǒ ) Ǔ ) ǒ ) Ǔƫ ) ǒ ) Ǔ

+ VIO2 1 ) R3 R1 –V

R3 IO1 R1 VI–

R7

R5

R7

R7

R5

1

R7

+ U1A –

1

R6 R4

R6 R4

R2 R6 R1 R4

R6 1 R4

R4

R6

10 kΩ

10 kΩ

R2 R1

V

IO3

1

R6 R4

100 kΩ R2 –

200 kΩ 10 turn

10 MΩ

2 kΩ

+

AV = 2 to 100

10 MΩ

R1

VO

U2A

VCC+

R3 100 kΩ –

– U1B

U2B 10 kΩ

10 kΩ

Offset Null

+

+

VI+

82 kΩ R7

R5

1 kΩ 0.1 µF

NOTE A: U1 and U2 = TL05xA; VCC± = ±15 V.

82 kΩ VCC–

Figure 86. Instrumentation Amplifier

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43

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION high input impedance log amplifier The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low temperature coefficient. In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-µA temperature-stable current source that sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and Q2 (see Figure 88). The output voltage is given by the following equation: V

O

ƪ ƫ ȱȧȲ ǒ

+ – 1 ) R6 R5

kT q

V

In

R1

I 10 –6

1

Q1

ȳȧ Ǔȴ

+

where k 1.38 10 –23, q and T is Kelvin temperature

+ 1.602

10 –19,

Q2 R4 2.5 MΩ

2N2484

VI

+ U1A _

R2 10 kΩ

15 V

R1

+ _U1C C1

+ U1B _

10 kΩ

+ U1D _ R6

150 pF

R3

R5 10 kΩ

270 kΩ

–15V

10 kΩ

IC1

NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference

Figure 87. Log Amplifier

AVD – Differential Voltage Amplification – dB

–0.1

–0.15

–0.2

–0.25

–0.3

ÁÁ ÁÁ ÁÁ

–0.35

–0.4 0

1

2

3

4

5

6

7

8

9

10

f – Frequency – Hz

Figure 88. Output Voltage vs Input Voltage for Log Amplifier

44

POST OFFICE BOX 655303

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VO (see equation above)

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION analog thermometer By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through the temperature-sensing diode D1. For this section of the circuit to operate correctly, the TL05x must use split supplies, and R3 must be a metal-film resistor with a low temperature coefficient. The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature. Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains constant. Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F). IC1

150 pF U1A +

10 kΩ (see Note B)

R3

D1 (see Note A)

10 kΩ

10 kΩ

10 kΩ



100 kΩ

R12

+15 V

R7 5 kΩ

R5 5 kΩ



R1

R9

S1 (see Note C)

VO (see Note D)

–15 V

+15 V

R2

U2B +

+ U1B – R6

C1

R8

100 kΩ

10 kΩ R10

– U2A

NOTES: A. B. C. D. E.

+

IC2

10 kΩ

R4 50 kΩ

R11 10 kΩ

Temperature-sensing diode ≈ (–2 mV/°C) Metal-film resistor (low temperature coefficient) Switch open for °F and closed for °C VO α temperature; 10 mV/°C or 10 mV/°F U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference

Figure 89. Analog Thermometer

POST OFFICE BOX 655303

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45

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION voltage-ratio-to-dB converter The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For measuring two input signals of different frequencies, extra filtering should be added after the rectifiers. The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing the logarithmic conversion also requires two well-matched npn transistors. The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-kΩ potentiometer on the input of U3C calibrates the zero-dB reference level. The following equations are used to derive the relationship between the input voltage ratio, expressed in decibels, and the output voltage.

X dB

X dB

V

BE(Q1)

ƪƫ

+ 20 log + 8.686 + kTq

ȱȧ ǒ Ǔ ǒ Ǔȳȧ Ȳ ȴ ƪ ǒ Ǔ ǒ Ǔƫ V V

A B

+ 20

ƪ ƫ In V

A

In V

– V A B In (10)

– In V

V

In

A R I

V

S

DVBE + VBE(Q1) –VBE(Q2) + X dB where k

+ 8.686 kTńq

+ 1.38

B

ƪ

V

BE(Q1)

10 –23, q

–V

+ 1.602

BE(Q2) kT q

BE(Q2)

+ kTq

ƪ ƫ V

In

R

B I

ƪ ǒ Ǔ ǒ Ǔƫ In V

– In V

ƫ+ ƪ A

336 V

S

B

BE(Q1)

–V

BE(Q2)

ƫ

at 25°C

10 –19, and T is Kelvin temperature

This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain 100 mV/dB.

46

POST OFFICE BOX 655303

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TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION R2 VA

+ U1A _

R1 20 kΩ

2N2484

10 kΩ + U1B _

R6

+ U1C _

D1

10 kΩ

R5

+ U2A _

20 kΩ

R7 + U3A _

10 kΩ

R18

R20

10 kΩ

10 kΩ

R16

+ U3D _

16.3 kΩ

R9 VB

+ _U1D

10 kΩ R4 10 kΩ

R3 30 kΩ

R8

Q1

VO

R76

2N2484

10 kΩ

16.3 kΩ

+ U2B _

+ U2C _

D2

R13 10 kΩ

R12

+ U2D _

10 kΩ R11 10 kΩ

R10 30 kΩ

10 kΩ

R19

+ U3B _

Q2

R14

10 kΩ R21 10 kΩ

15 V

82 kΩ

+ U3C _

1 kΩ C1

82 kΩ –15 V NOTE A: U1A through U3D = TL05xA, VCC± = ±15 V. D1 and D2 = 1N914.

Figure 90. Voltage Ratio-to-dB Converter

VO – Output Voltage – V

2

1

0

–1

–2 0

1

2

3

4 5 6 Ratio – VA/VB

7

8

9

10

Figure 91. Output Voltage vs the Ratio of the Input Voltages for Voltage-to-dB Converter

POST OFFICE BOX 655303

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47

TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003

APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model-generation software used with Microsim PSpice. The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the TL05x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

D D D D D D

D D D D D D

Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification

Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit

NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 3

VCC+

9 RSS 10 J1

DP

VC J2

IN+ 11

VAD

DC

12 C1

RD1

R2 – 53

HLIM



+

C2

6



+

+ GCM

GA

VLIM 8





RO1

DE

5

+ VE

OUT

.SUBCKT TL05x 1 2 3 4 5 C1 11 12 3.988E–12 C2 6 7 15.00E–12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 2.875E6 –3E6 3E6 3E6 –3E6 GA 6 0 11 12 292.2E–6 GCM 0 6 10 99 6.542E–9 ISS 3 10 DC 300.0E–6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3

RD1 4 11 3.422E3 RD2 4 12 3.422E3 R01 8 5 125 R02 7 99 125 RP 3 4 11.11E3 RSS 10 99 666.7E6 VB 9 0 DC 0 VC 3 53 DC 3 VE 54 4 DC 3.7 VLIM 7 8 DC 0 VLP 91 0 DC 28 VLN 0 92 DC 28 .MODEL DX D (IS=800.0E–18) .MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6 + VTO=–.1) .ENDS

Figure 92. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates.

48



RD2

54 4



7

60

+ –

+ DLP

91 + VLP

90

RO2

VB

IN–

VCC–

92

FB



+

ISS

RP 2

3

DLN

EGND +

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

VLN

PACKAGE OPTION ADDENDUM www.ti.com

18-Feb-2005

PACKAGING INFORMATION Orderable Device

Status (1)

Package Type

Package Drawing

Pins Package Eco Plan (2) Qty

TL051ACD

ACTIVE

SOIC

D

8

75

TL051ACP

ACTIVE

PDIP

P

8

50

TL051AID

OBSOLETE

SOIC

D

8

TL051AIP

OBSOLETE

PDIP

P

8

TL051CD

ACTIVE

SOIC

D

8

75

TL051CDR

ACTIVE

SOIC

D

8

2500

TL051CP

ACTIVE

PDIP

P

8

50

Lead/Ball Finish

MSL Peak Temp (3)

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

None

Call TI

Call TI

None

Call TI

Call TI

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL051ID

OBSOLETE

SOIC

D

8

None

Call TI

Call TI

TL051IDR

OBSOLETE

SOIC

D

8

None

Call TI

Call TI

TL051IP

OBSOLETE

PDIP

P

8

None

Call TI

Call TI

TL052ACD

ACTIVE

SOIC

D

8

75

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052ACDR

ACTIVE

SOIC

D

8

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052ACP

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL052AID

ACTIVE

SOIC

D

8

75

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052AIDR

ACTIVE

SOIC

D

8

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052AIP

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL052AMFKB

OBSOLETE

LCCC

FK

20

None

Call TI

Call TI

TL052AMJGB

OBSOLETE

CDIP

JG

8

None

Call TI

Call TI

TL052CD

ACTIVE

SOIC

D

8

75

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052CDR

ACTIVE

SOIC

D

8

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052CP

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL052CPSR

ACTIVE

SO

PS

8

2000

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

TL052ID

ACTIVE

SOIC

D

8

75

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052IDR

ACTIVE

SOIC

D

8

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL052IP

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL052MFKB

OBSOLETE

LCCC

FK

20

None

Call TI

Call TI

TL052MJG

OBSOLETE

CDIP

JG

8

None

Call TI

Call TI

TL052MJGB

OBSOLETE

CDIP

JG

8

None

Call TI

Call TI

TL054ACD

ACTIVE

SOIC

D

14

Pb-Free (RoHS)

CU NIPDAU

50

Addendum-Page 1

Level-2-250C-1 YEAR

PACKAGE OPTION ADDENDUM www.ti.com

18-Feb-2005

Orderable Device

Status (1)

Package Type

Package Drawing

Pins Package Eco Plan (2) Qty

TL054ACDR

ACTIVE

SOIC

D

14

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054ACN

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL054AID

ACTIVE

SOIC

D

14

50

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054AIDR

ACTIVE

SOIC

D

14

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054AIN

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL054AMFKB

OBSOLETE

LCCC

FK

20

None

Call TI

Call TI

TL054AMJB

OBSOLETE

CDIP

J

14

None

Call TI

Call TI

TL054CD

ACTIVE

SOIC

D

14

50

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054CDBR

ACTIVE

SSOP

DB

14

2000

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

TL054CDR

ACTIVE

SOIC

D

14

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054CN

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL054CNSR

ACTIVE

SO

NS

14

2000

Pb-Free (RoHS)

CU NIPDAU

Level-2-260C-1 YEAR/ Level-1-235C-UNLIM

TL054ID

ACTIVE

SOIC

D

14

50

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054IDR

ACTIVE

SOIC

D

14

2500

Pb-Free (RoHS)

CU NIPDAU

Level-2-250C-1 YEAR

TL054IN

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

Level-NC-NC-NC

TL054MFKB

OBSOLETE

LCCC

FK

20

None

Call TI

Call TI

TL054MJ

OBSOLETE

CDIP

J

14

None

Call TI

Call TI

TL054MJB

OBSOLETE

CDIP

J

14

None

Call TI

Call TI

Lead/Ball Finish

MSL Peak Temp (3)

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com

18-Feb-2005

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8

5

0.280 (7,11) 0.245 (6,22)

1

0.063 (1,60) 0.015 (0,38)

4 0.065 (1,65) 0.045 (1,14)

0.310 (7,87) 0.290 (7,37)

0.020 (0,51) MIN

0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN

0.023 (0,58) 0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36) 0.008 (0,20)

4040107/C 08/96 NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MECHANICAL DATA MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

18

17

16

15

14

13

NO. OF TERMINALS **

12

19

11

20

10

A

B

MIN

MAX

MIN

MAX

20

0.342 (8,69)

0.358 (9,09)

0.307 (7,80)

0.358 (9,09)

28

0.442 (11,23)

0.458 (11,63)

0.406 (10,31)

0.458 (11,63)

21

9

22

8

44

0.640 (16,26)

0.660 (16,76)

0.495 (12,58)

0.560 (14,22)

23

7

52

0.739 (18,78)

0.761 (19,32)

0.495 (12,58)

0.560 (14,22)

24

6 68

0.938 (23,83)

0.962 (24,43)

0.850 (21,6)

0.858 (21,8)

84

1.141 (28,99)

1.165 (29,59)

1.047 (26,6)

1.063 (27,0)

B SQ A SQ

25

5

26

27

28

1

2

3

4 0.080 (2,03) 0.064 (1,63)

0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

4040140 / D 10/96 NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004

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MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60) 0.355 (9,02) 8

5

0.260 (6,60) 0.240 (6,10)

1

4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38) Gage Plane

0.200 (5,08) MAX Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54) 0.021 (0,53) 0.015 (0,38)

0.430 (10,92) MAX

0.010 (0,25) M

4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN 0,38 0,22

0,65 28

0,15 M

15

0,25 0,09 8,20 7,40

5,60 5,00

Gage Plane 1

14

0,25

A

0°–ā8°

0,95 0,55

Seating Plane 2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01 NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150

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