WWW.VIDYARTHIPLUS.COM DIGITAL ELECTRONICS QUESTION BANK UNIT – 1 MINIMIZATION TECHNIQUES AND LOGIC GATES 2 marks 1. What happens when all the gates in a two level AND-OR gate network is replaced by NOR gates? 2. Implement Y AB A ( B C ) using NAND gates only. 3. If A and B are Boolean variables and if A=1 and A B 0 , find B. 4. Express the switching function fAB = A in terms of minterms. 5. Apply Demorgan’s theorems to simplify A BC . 6. Express x yz as the sum of minterms. 7. What is prime implicant? 8. What are ‘minterms’ and ‘maxterms’? 9. Why binary number system is used in digital system? 10. Define the laws of Boolean algebra. 11. For a switching function of ‘n’ variables, how many distinct minterms and maxterms are possible? 12. State two absorption properties of Boolean algebra. 13. State Demorgan’s theorem 14.Draw an active tri-state buffer and write its truth table14. 15. Define canonical form. Express F BC AC in a canonical SOP form. 16. Write down Fan in & Fan out of a standard TTL IC 17. What is Propagation Delay of a gate? 18.List out the major categories of logic circuits 19.Express F= A+B’C as sum of minterms 20.Implement F= (AB’+ A’B)(C+D’) with only NOR gates. 21. Find the complement of x + yz 22. State and prove consensus theorem. 23.Implement AND and OR gate using NAND gate. 24. . Find the binary representation of decimal 125. 25. Complement the expression X(Y'+Z'). WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 26. Convert Y= A+BC'+AB+A'BC into canonical form 27. What is meant by ‘essential prime-implicant’? 28.Obtain the complement of f=wx’y+xy’=wxz using de morgan’s theorem 29.Show that A+A’B=A+B using the theorems of Boolean algebra 30.What is the advantage of gray codes over the binary number sequence 31.Simplify the following Boolean function i)x(x’+y) ii)xy+x’z+yz 32.Convert the following function into sum of product form (AB+C)(B+C’D) 33.What is the significance of high impedance state in tri-state gates
I6 Marks questions 1.State and prove the postulates, theorems of Boolean algebra. 2.Use QM method to simply the Boolean expression(x1,x2,x3,x4,x5)= ∑(0,1,4,5,16,17,21,25,29) (NOV’2010) 3.Use Quine McClusky method to obtain the minimal sum for the following function. F(X1X2X3X4) = ∑ (0, 1, 3, 6, 7, 14, 15) (April 2003) 4.Simplify the function using Karnaugh map. (i) F (ABCD) = ∑ (0, 1, 2, 4, 5, 7, 11, 15) (8mark) (ii) F (WXYZ) = ∑ (2, 3, 10, 11, 12, 13, 14, 15)
(8mark) (April 2003)
4. (i) State and prove demorgan’s theorem and expand the function F = ( (( A B )C C D )
(ii) Simplify the following switching function using karnaugh map, F(A,B,C,D) = ∑ (0,5,7,8,9,10,11,14,15) + Φ (1,4,13)
5..i) Simplify the following Boolean function using 4 variable map F(w,x,y,z)= ∑(2,3,10,11,12,13,14,15)
ii)Draw a NAND logic diagram that implements the complement of the following function F(A,B,C,D)= ∑(0,1,2,3,4,8,9,12)
6.Simplify the Boolean function using K-map and tabular methods. Compare the methods. F (A, B, C, D) =∑m(4,5,6,7,8)
d (A, B, C, D) = ∑m(11,12,13,14,15).
7.Implement using only NAND gates (i) Express the function f(x, y, z) = XY X Z as a product of sum WWW.VIDYARTHIPLUS.COM
(4 marks) V+ TEAM
WWW.VIDYARTHIPLUS.COM (ii) Express the following function as the minimal sum of products, using a K-map
F (a,b,c,d) =∑m(0,2,4,5,6,8,10,15) + ∑Φ(7,13,14)
8.Implement the following with either NAND gate or NOR gate gates. Use only 4 gates. Only the normal inputs are available. (i) d = WYZ
(ii) F = W XZ WYZ X WX Y Z (8mark) 9. Using tabulation method simplify the Boolean function F(w,x,y,z)=Σ(1,2,3,5,9,12,14,15) which has the don’t care conditions d(4,8,11). 10.Reduce the Boolean function using K-map technique and implement using gates f(w,x,y,z)= Σ(0,1,4,8,9,10) which has the don’t care conditions d(w,x,y,z)= Σ(2,11). 11.Simplify the following Boolean function by using the tabulation method F= Σ(0,1,2,8,10,11,14,15). 12.i) Simplify the following Boolean function F(w,x,y,z)= Σ(1,3,7,11,15)that has the don’t care conditions d(w,x,y,z)= Σ(0,2,5). 13. Simplify the following Boolean function using tabulation method F(A,B,C,D) = ∑m(0,2,3,6,7,8,10,12,13) 14.Simplify the following using tabulation method F(a,b,c,d)= ∑m(1,2,3,5,9,12,14,15)+ ∑d(4,8,11) 15.Find the reduced form POS form of the following equation F(a,b,c,d)= m(1,3,7,11,15)+ d(0,2,5).Implement using NAND logic 16.simplify the following using the Quine-Mcclusky minimization technique D=f(a,b,c,d)= ∑(0,1,2,3,6,7,8,9,14,15) 17.(i) Minimize the switching function F(a,b,c,d)= ∑(1,4,5,7,13)+ ∑d(0,6,14,15) on a 4 variable Karnaugh map (ii) Express x+yz as the product of maxterms 18.Find the MSP form of F(w,x,y,z)= ∑(1-3,5-10,12-14) using the Quine-Mcclusky minimization technique 19.i)Simplify the following using map method F(a,b,c,d)= ∑m(0,2,4,6,8,10,12,14)
Find the DeMorgan Equivalent of the function F=XYZ+XZ+X’Y’+YZ
20. simplify the following 5 variable boolean expression using the Quine-Mcclusky minimization technique F(a,b,c,d)= ∑(0,1,9,15,24,29,30)+d(8,11,31)(16) 21.Determine the minterm sum of product form of the switching function WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM F=∑(0,1,4,5,6,11,14,15,16,17,20,21,22,30,32,33,36,37,48,49,52,53,59,63) UNIT – 2 COMBINATIONAL CIRCUITS 2 marks 1. Define half adder and full adder. 2. Define half subtractor and full subtractor. 3. How logic circuits of a digital system are classified? 4. What is a combinational circuit? Give an example. 5. Write an expression for borrow and difference in a full subtractor circuit 6. List the advantage of look ahead carry? When should it be used? 7. Distinguish between Decoder and Demultiplexer 8. What are the applications of magnitude comparator? 9.Generate an odd and even parity for the information 1000 111 10 Write down the truth table of a half subtractor 11. Draw the half adder circuit. 12. Write down the truth table of a. full subtractor. 13.Draw full adder circuit 14..Write down the truth table of a full adder 15. Define combinational logic 16. Explain the design procedure for combinational circuits 17.Convert gray code 101011 into its binary equivalent. 18. What are called don’t care conditions? 19. Define magnitude comparator? 20. What are the two steps in Gray to binary conversion? 21.Compare the serial and parallel adder 22.Define look ahead carry addition 2.3Relate carry generate, carry propagate, sum and carry-out of a Carry look ahead adder. 24. Build a 4:1 mux using only 2:1 mux 25.What is Tristate buffer? Give its applications. 26.Draw the circuit of 2 bit even and odd parity checker and generator 27.What is a decoder? WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 28. What do you mean by encoder? 29. What is a priority encoder? 30. What is a multiplexer? 31.Give applications of MUX: 32.How can a decoder be converted into a demultiplexer? 33.Implement the logic function f = AB + A B using a suitable multiplexer. 34. Explain how parity can be used for error detection? 35.What is the difference between decoder and Demultiplexers? 16 MARK QUESTIONS 1.Design a BCD to Gray code converter. Use don’t cares 2.Design a half adder and full adder circuits . 3.Design a half subractor and design a subractor 4.Design a 4-bit binary to BCD code converter. 5. Construct a 4-bit binary to gray code converter circuit and discuss its operation. 6.Design a combinational circuit to convert Excess-3 code to BCD code. 7.i) Design an 8X1 MUX using only 2X1 MUX
ii) Design a circuit to carry out both addition and subtraction
8.Design a BCD adder to add two BCD digits 9.Design a combinational circuit that accepts 3 bit binary number and converts it to excess 3 code. 10. Design a circuit to compare two four bit numbers 11. Design a Gray to BCD code converter 12. Design a combinational circuit to convert BCD code to Excess-3 code 13. Design a combinational logic circuit to compare two 2- bit binary numbers A and B and to generate the outputs AB 14.i)Realize F(w,x,y,z)=S(1,4,6,7,8,9,10,15) using 4 to 1 Mux ii) Design a binary multiplier circuit
15. a(i) Design an 8x1 MUX using only 2x1 MUX (8) (ii) Design a circuit to carry out both addition and subtraction (8) 16.Design and implement the conversion circuit for BCD to Excess 3 code (16) 17 .i).Design a combinational circuit that generates the 9’s complement of a BCD digit (8) NOV’2010 ii) Expalin the operation of carry lookahead adder with neat diagram. (8) 18.i) Define fan-in, fan –out and Noise margin (6) NOV’2010 WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM ii) Design a combinational system that produces the product of 2 binary number A=(A1,A0) X B= (B2,B1,B0) (10)
UNIT III SEQUENTIAL CIRCUITS 1.Differentiate between synchronous and asynchronous circuit? 2.List the applications of flip-flop 3.Name the different types of shift registers 4.Define state diagram 5.How should a JK flip flop be connected to function as a divide by 2-element? 6.What is a sequential circuit? 7. What is flip-flop also known as a latch? 8. Distinguish between latch and flip-flop. 9 . Why D latch is called transparent latch. 10. What is triggering? 11.What is meant by the term “edge triggered”? 12.What is state equation? 13.What is state table? WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 14.What is state diagram? 15. What is meant by the term state-reduction? 16. Write the flip-flop excitation tables for JK and T FF. 17. Mention the two types of circuit that include flip-flops. 18. What is register? 19. What is counter? 20. What is a shift register? 21. Define binary counter. 22. Define ripple counter. 23. Define binary count-down counter. 24. What is decade counter? 25.List out at least four applications of FF’s 26.What are the principal between synchronous and asynchronous counters? 27.Distinguish between combinational logic circuits and sequential logic circuits? 28.What are the advantages of shift registers? 29.What are the various types of triggering of FF’S 30.Derive the characteristic equation of T flip flop 31.What is the minimum of Flip flops required to build a counter of modulus 8 32.Draw the logic diagram for T flip flop. 33. What is modulo n counter? 34. How many states are there in a 3 bit ring counter? What are they? 35.What are the states of 4 bit ring counter? 36. Draw the internal circuit of a NOR gate latch and derive the truth table. 37. Discuss the operation of SR flip flop with help of the state diagram.
16 MARK QUESTIONS 1. i) Provide the characteristic table, characteristic equation and excitation table of D flip flop and JK flip flop (6) ii) Explain the operation universal shift register with neat block diagram
2. With a neat state diagram and logic diagram , design and explain the sequence of states of BCD counter (16) 3. Draw the circuit and explain the working operation of JK Master Slave flip-flop WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 4. Explain the various steps in the analysis of synchronous sequential circuits with suitable example. 5. Using D flip-flops, design a synchronous counter which counts in the sequence 000, 001, 010, 011, 100, 101, 110, 111, 000 6. Using JK flip-flops, design a synchronous counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000…… 7. Design a binary counter using T flip-flops to count pulses in the following sequence (i) 000, 001, 010, 011, 100, 101, 110, 111, 000 (ii) 000, 100, 111, 010, 011, 000
8. Explain the functional operation of a 4 bit binary ripple counter with its logical diagram 9. Explain the working of Master-slave flip-flop. 10. i) Draw a 4 bit serial in serial out shift register and draw its waveforms. (8) ii). Draw a 4 bit serial in parallel out (SIPO) and explain its operation. (8) 11. Explain the operation of BCD counter. 12. Design an Asynchronous BCD down counter using J-K flip=flop and verify its operation. 13. Design a synchronous mod-8 down counter and implement it. 14. Design and explain the working of a up-down ripple counter 15. (i) Explain the operation of D type edge triggered flip flop. (8 marks) (ii) How can a D flip flop converted into a T flip flop.
16. Using JK flip-flops, design a synchronous counter which counts in the sequence 2,6,1,7,5,4 and repeat. 17. Design a Mod 5 Asynchronous counter draw the wave forms. (8marks) 18. Using RS flip-flops, design a Parallel counter which counts in the sequence 000, 111, 101, 110, 001, 010, 000…… 19. .i) Draw the logic diagram for a master –slave JK flip flop and explain. ii) Draw the four bit Johnson counter and explain the operation 20. Draw and explain the logic diagram of up/down counter
UNIT IV MEMORY DEVICES 2 marks 1. How is the design of combinational and sequential logic circuits possible with PLA? 2. Is the PAL same as the PLA? Justify. or Distinguish between PAL and PLA 3. Define priority encoder? WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 4. What is meant by ‘static’ and ‘dynamic’ memories? 5. What is FPLA? . 6. Name any two random access memories. 7. Differentiate between SRAM and DRAM. 8. What is PLA? 9.Give any two application of PLA’S 10.What is a decoder and obtain the relation between the number of inputs ‘n’ and outputs ‘m’ of a decoder 11. List basic types of programmable logic devices. 12.Define address and word: 13. What are the types of ROM 14. What is programmable logic array? How it differs from ROM? 15. What is field programmable logic array? 16.Mention some major applications of multiplexers 17.Mention the uses of decoders. 18.Write data flow description of a 2 to 1 line MUX using conditional operator. 19.Implement the logic function f = ∑ (0,2,3,6) using a Decoder. 20.How can a multiplexer be used to convert 8 bit parallel data into serial form. 21. What is the maximum range of a memory that can be accessed using 10 address lines? 16 MARK QUESTIONS 1.Explain the basic structure of 256x 4 static RAM with neat sketch (8) 2. Write a note on (i) MOSFET RAM cell (8) (ii) Dynamic RAM cell 3. i) Explain read and write operation of memory with timing waveforms. ii) Write a note on RAM. (8)
4. i) Draw a PLA circuit to implement the functions F1=A’B+AC’+A’BC ; F2= (AC+AB+BC)’ (8) ii) write a note on FPGA. (8)
5.A combinational circuit is defined by the functions F1 = ∑m(3,5,7)
F2 = ∑m(4,5,7)
Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs. 6. Implement binary to excess 3 code converter using ROM. WWW.VIDYARTHIPLUS.COM
(16) V+ TEAM
WWW.VIDYARTHIPLUS.COM 8.Tabulate the PAL programming table for the four Boolean functions listed below. A(x, y, z) = ∑ (1, 2, 4, 6), B(x, y, z) = ∑(0, 1, 6, 7) C(x, y, z) = ∑(2, 6), D(x, y, z) = ∑(1, 2, 3, 5, 7) (16) 9. A combinational circuit is defined by the functions
F1(A,B,C)=Σ(3,5,6,7) F2(A,B,C)=Σ(0,2,4,7) implement the circuit with a PLA. 10. A combinational circuit is described by the functions F1 =∑m(3,4,5,7,10,14,15), F2=∑m(1,5,7,11,15) Implement the circuit with a PLA having 4inputs ,6 product terms and two outputs 12.A combinational circuit is defined by the functions F1 = ∑m(3,5,7) F2 = ∑m(4,5,7) Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs. 13.A combinational circuit is defined by the functions F1 = ∑m(1,3,5) F2 = ∑m(5,6,7) Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs.
UNIT – V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS 1. Define asynchronous sequential circuit. 2. State the difference between the synchronous and asynchronous sequential circuits. 3. What is a fundamental mode asynchronous sequential circuits. 4. What is a critical race? Why should it be avoided? 5. Define cycle. 6. Define Hazard. 7. Define race, critical race and non-critical race. 8. Define a primitive flow table. 9. What is Static 1 Hazard? 10. Define static Hazard. 11. Define Glitch. 12. What is a dynamic hazard? WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM 13. What is essential hazard? 14. What are Mealy and Moore machines? 15. What is a race? 16. What is a cycle? 17. What is shared row state assignment? 18. Mention any advantage and disadvantage of asynchronous sequential circuits 19. Define static 0-hazard,static 1-hazard and dynamic hazard 20. What is the difference between Mealy machine and Moore machine 21.Explain the procedure for state minimization. 22. What is pulse mode circuit? 23. What are the types of Hazards? 24.What are the assumptions made for pulse mode circuit? 25. What are the assumptions made for fundamental mode circuit?
16 MARK QUESTIONS 1. i)Give examples for critical race and cycle and explain ii) Describe the hazards with neat circuit diagram. 2.
Give the hazard free realization for the following functions. f(a, b, c, d) = m (0, 2, 6, 7, 8, 10, 12)
3.Design an asynchronous sequential circuit that has two inputs X2 and X1 and one output z. When x1 = 0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to zero . (16) 4.An asynchronous sequential circuit has two internal states and one output.The excitation and output function describing the circuit are as follows.
Y1 x1 x 2 x1 y 2 x 2 y1 Y2 x 2 x1 y1 y 2 x1 y1 Z x 2 y1 5. i)Give hazard-free realization for the following Boolean function F(A,B,C,D)=Σm(1,3,6,7,13,15) ii) Summarize the design procedure for asynchronous sequential circuit. 6.An asynchronous sequential circuit is described by the following excitation and output function. Y=X1X2+(X1+X2)Y i) Draw the logic diagram WWW.VIDYARTHIPLUS.COM
WWW.VIDYARTHIPLUS.COM ii) Derive the transition table and output map iii) Describe the behavior of the circuit. 7. An asynchronous network has two inputs and one output. The input sequence X1X2 =00, 01,11causes the output to become 1.The next input change then causes the output to return to 0. No other input sequence will produce a 1 output. Construct the state diagram using primitive flow table (16) 8.a)Design a circuit with inputs A and B to give an output Z equal to 1 when AB=11 but only if A becomes 1 before B, by drawing total state Diagram, primitive flow table and output map in which transient state is Included. b) Design a circuit with primary inputs A and B to give an output Z equal to 1 When A becomes 1 if B is already 1.Once Z=1 it will remain so until A goes to c) Draw waveform diagram, total state diagram, primitive flow table for designing the circuit. 9. An asynchronous circuit described by the following excitation and output function Y=X1.X2+(X1+X2).Y Z=Y Draw the logic diagram of the circuit. Derive the transition table and output map. Describe the behavior of the circuit 10.Design a asynchronous sequential circuit with 2 inputs X and Y and with one output Z whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X. use SR latch for implementation of the circuit 11. What is a merger graph .How it is used to reduce states in the incompletely specified table 12. What are the problems in asynchronous circuits and what are essential hazards and static hazards how it can be eliminated 13. Design T flip flop from logic gates. 14..Give the hazard free realization for the following functions. (i) NAND gates (ii) NOR gates f(a, b, c, d) = m (1,5,7,14,15) 15. Design a sequence Detector circuit with a single input line and a single output line. Whenever the input consists of the sequence 101 , the output should be 1. For example, if the input is 00110101…,then the output is 00000101… in other words,over lapping sequences are allowed. Use any type of flip flop. (16) 16.(i) .Give the hazard free realization for the following functions. f(a, b, c, d) = m (1,3,6,7,13,15) WWW.VIDYARTHIPLUS.COM
(8marks) V+ TEAM
WWW.VIDYARTHIPLUS.COM (ii) Summarize the design procedure for asynchronous sequential circuit. ( 8marks ) 17. An asynchronous circuit described by the following excitation and output function X=(Y1.Z1’W2) X + ( Y1’Z1W2’) S= X’ Draw the logic diagram of the circuit. Derive the transition table and output map. Describe the behavior of the circuit 18.Explain essential , static and dynamic Hazards in Digital circuit. Give the hazard free realization for the following functions. F(I,J,K,L) = m (1,3,4,5,6,7,9,11,15) 19 Design an asynchronous circuit using JK FF that will O/P only the first pulse received and will ignore any other pulses (16) 20. i) Differentiate critical races from non-critical races. (6) NOV’2010 ii) Explain the steps involved in the reduction of state table.