ES9023 datasheet - myL8test [PDF]

Confidential - Shaw Electronics

CONFIDENTIAL ADVANCE INFORMATION

ES9023 Premier Stereo DAC with 2Vrms Driver Datasheet

Analog Reinvented Device

Description

ES9023

Sabre Premier Stereo DAC with 2Vrms Op-Amp Driver

DNR (dB) 112

Power Supply (Output Level) +3.6V (2Vrms) +3.3V (1.9Vrms)

No DC-blocking capacitor √

Pop-Noise Free √

Package 16-SOP

The ES9023 is a 24-bit stereo audio DAC with an integrated 2Vrms op-amp driver. Powered by the industry proven Sabre DAC technology, the ES9023 combines best-sounding audio with lowest system cost and highest performance into the ideal D/A converter for line-level output applications such as Blu-ray players, CD/DVD players, set-top boxes, digital TVs and audio receivers.

With patented HyperstreamTM architecture and Time Domain Jitter Eliminator, the ES9023 delivers jitter-free studio quality audio with 112dB DNR.

Using an integrated charge pump to generate the negative supply, the ES9023 can operate from a single AVCC supply to drive a ground-referenced 2Vrms output, eliminating the need for output dc-blocking capacitors. Optionally, the output level can be adjusted by using an external resistor, allowing for output level below 2Vrms. Pop-noise is eliminated through a comprehensive suppression on power up/down, mute, reset, loss of power or clock. Dedicated control/status pins allow easy system integration without the need for microcontroller programming.

FEATURE

Sabre DAC and 2Vrms op-amp driver integration Patented HyperStreamTM and Jitter Elimination Architecture Adjustable output level Ground reference output Pop-noise suppression Dedicated control/status pins I2S or left-justified select Soft mute enable Zero detect output Charge pump for negative supply Low power consumption in 16-SOP

BENEFIT

Lowest system cost by minimizing external components Highest performance Best sounding audio – powered by Sabre DAC technology Best dynamic range: 112dB Jitter Immune Allow designer to customize output level (up to 2Vrms) based on application requirements via an external resistor Reduce cost by eliminating blocking capacitors Pop-free on power up/down, mute and reset Easy to use – no programming required

Single AVCC simplifies power supply Simply power supply and reduce PCB size

ESS TECHNOLOGY, INC. 48401 Fremont Blvd., Fremont, CA 94538, USA Tel (510) 492-1088 • Fax (510) 492-1098


CONFIDENTIAL ADVANCE INFORMATION Rev. 0.1

September 17, 2010

ES9023 Datasheet

FUNCTIONAL BLOCK DIAGRAM ES9023

Control/Status

BCK LRCK SDI

PCM Interface

Oversampling Filter

Jitter Reduction

HyperStream DAC (2x)

2Vrms Op-Amp Driver (2x)

AOUTL AOUTR

MCLK

VEE

AVSS

AVDD

CN

CP

Power Supply & Charge Pump

APPLICATION DIAGRAM

Blu-Ray Player

3.3V

DVD Player

L

Audio

Audio Out (2Vrms)

Processor ES9023

R

Home Theater Receiver

PC Pro-Audio Sound Card


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September 17, 2010


ES9023 Datasheet

PIN LAYOUT BCK LRCK SDI DIF AVCC VREG AOUTL AOUTR

1 2 3 4 5 6 7 8

ES9023 16SOP

16 15 14 13 12 11 10 9

ZD MUTE_B DGND MCLK AGND NEG CN CP

PIN DESCRIPTION

3

Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Name BCK LRCK SDI DIF AVCC VREG AOUTL AOUTR CP CN NEG AGND MCLK DGND MUTE_B ZD

Type I I I I P P O O I I P P I P I O

Pin Description I2S Bit Clock I2S L/R (Word) Clock I2S Serial Data Input Input to select Left Justified or I2S data AVCC Power supply Analog Reference Output Left Analog Output Right Analog Output Positive Terminal of External Charge Pump Capacitor Negative Terminal of External Charge Pump Capacitor Negative Supply (Internally Generated) Analog Ground Master (System) Clock Ground Active Low Mute Input Zero Detect Output




September 17, 2010

ES9023 Datasheet

FUNCTIONAL DESCRIPTION I2S Decoder: Run by the I2S bit clock, typically a 64FS clock, the I2S Decoder translates the incoming I2S data to 24-bit signed PCM data. If a smaller bit-width is used, the remaining is ‘zero-padded’. Driving the DIF pin low will set the DAC in I2S mode while driving the pin high will set the DAC in LJ mode. Below is a timing diagram illustrating the two modes (LJ and I2S) utilized by the ES9023.

Zero Detect: The zero-detect function outputs an external status signal (ZD) based on a zero-valued input for a given number of clock cycles. The ZD output signal is set high when both data channels are zero for 8192 LRCK cycles.

MCLK Asynchronous mode: MCLK must be > 192*fs. Synchronous mode: Please see table below for supported configurations.

LRCK (kHz) fs 32 44.1 48 88.2 96 176.4 192

128fs 11.2896 12.288 22.5792 24.576

192fs 16.9344 18.432 33.8688 36.864

MCLK (MHz) 256fs 384fs 512fs 12.288 16.384 11.2896 16.9344 22.5792 12.288 18.432 24.576 22.5792 33.8688 45.1584 24.576 36.864 49.152 45.1584 49.152 -

768fs 24.576 33.8688 36.864 -

1152fs 36.864 -

For best performance. 256fs or greater is recommended for 32kHz to 96kHz sampling.


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September 17, 2010


ES9023 Datasheet

MUTE_B Pin (Active Low) This input pin provides the ability to slowly ramp down the audio volume, and then enter low power standby. Release of mute will cause the ES9023 to emerge from low power mode and then slowly ramp the audio to provide a pop free startup.

MUTE_B 2097024 MCLK

(Internal) Attenuation

32768 2097024 MCLK MCLK

0dB

-∞ Power up delay

(Internal) Power Down

AOUT

Activation/release of the MUTE_B input pin initiates a sequence of internal events detailed below: • On assertion of the MUTE_B pin o The output signal will ramp to the -∞ level. The ramping takes 2097024 MCLK cycles. o After the output signal reaches the -∞ level, analog section is turned off and the ES9023 enters a low power standby state. • On release of the MUTE_B pin: o The ES9023 emerges from low power standby, starts an internal counter and activates the analog section o During the delay counter time, the internal charge pump and Vref stabilize. o When the counter reaches 32768 MCLK cycles, the audio signal is applied and the volume is ramped over 2097024 MCLK cycles to maximum.

To minimize pop noise at power up, an external circuit should be used to hold the MUTE_B pin asserted until tDMUTE (see p.10) after the power supply and MCLK are stabilized. • This can be realized using a reset IC, an MCU GPIO pin (default to low at power-up and changed to high by software later), or an RC time delay on this pin. • If MUTE_B pin is released too early, pop noise may occur due to the ramp-up of internal voltage.

~ ~

MCLK

~ ~

5

AVCC

Same time as AVCC or later tDMUTE

MUTE_B Assert MUTE_B until tDMUTE after the power supply and MCLK are stabilized




September 17, 2010

ES9023 Datasheet

DAC/OP-AMP: Each Hyperstream DAC is followed by an op-amp circuit for each channel. A pop suppression circuit is added on the output to eliminate any “pop” noise that may be heard during muting, un-muting, power-up and power-down sequences. In some conditions, pop noise may be audible. See the MUTE_B pin section above. Charge Pump (Negative Voltage Generation): This is an analog circuit required to generate an internal negative supply. With positive and negative supplies, the op-amp circuits will be able to generate a ground-referenced 2Vrms output.


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September 17, 2010


ES9023 Datasheet

APPLICATION DIAGRAM

7

100k

2.2uF

ES9023 10uF GND

R8: see p.9 for more details.




September 17, 2010

ES9023 Datasheet

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS PAREMETER Storage temperature Voltage range for 5V tolerant pins Voltage range for all other pins

RATING -65°C to 105°C -0.5V to +5.5V -0.5V to (AVCC+0.5V)

WARNING: Stress beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied. Exposure to the Absolute Maximum Ratings conditions for extended periods may affect device reliability. WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.

RECOMMENDED OPERATING CONDITIONS PAREMETER Operating temperature Power supply voltage

SYMBOL TA AVCC

CONDITIONS 0°C to 70°C 3.6V ± 5%, 31 mA nominal (*1), or 3.3V ± 5%, 23 mA nominal (*1)

Note

(*1) fs =48kHz, MCLK=27MHz, I2S input, output unloaded

DC ELECTRICAL CHARACTERISTICS Table 1 DC Electrical Characteristics SYMBOL VIH

VIL VCLKH VCLKL VOH VOL ILI ILO CIN CO CCLK

PARAMETER High-level input voltage

Low-level input voltage CLK high-level input CLK low-level input High-level output voltage Low-level-output voltage Input leakage current Output leakage current Input capacitance Input/output capacitance CLK capacitance

MIN 2

MAX AVCC

UNIT V

2 -0.3 2 -0.3 3

5.5 0.8 AVCC+0.25 0.8

V V V V V V µA

0.45 ±15 ±15 10 12 20

COMMENTS All inputs TTL levels except CLK and 5V tolerant input pins All 5V tolerant inputs All input TTL levels except CLK TTL level input IOH = 1mA IOL = 4mA

pF

fc = 1MHz

pF

fc = 1MHz


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ES9023 Datasheet

MCLK Timing tMCH

MCLK tMCL tMCY

Parameter MCLK pulse width high MCLK pulse width low MCLK cycle time MCLK duty cycle

Symbol TMCH TMCL TMCY

Min 9 9 20 45:55

Max

Unit ns ns ns

55:45

Audio Interface Timing tDCH

BCK DATACLK

SDI/LRCK DATA[8:1]

tDCL tDCY tDH Valid

tDS Invalid

Parameter BCK pulse width high BCK pulse width low BCK cycle time BCK duty cycle SDI/LRCK set-up time to BCK rising edge SDI/LRCK hold time to BCK rising edge

9

Invalid

Symbol tDCH tDCL tDCY tDS tDH

Min 20 20 44 45:55 2 2

Max

Unit ns ns ns

55:45 ns ns




September 17, 2010

ES9023 Datasheet

ANALOG PERFORMANCE Test Conditions (unless otherwise stated) 1. 2. 3.

TA=25oC, AVCC=3.6V, fs =44.1kHz, MCLK=27Mhz, 24-bit data, RL≥10kΩ, Signal Frequency=1kHz SNR/DNR: A-weighted over 20-22kHz in averaging mode THD+N: un-weighted over 20-22kHz bandwidth

PARAMETER SYMBOL PCM sampling rate fS Mute Delay tDMUTE DYNAMIC PERFORMANCE DNR (A-weighted) THD+N Interchannel Isolation DC Accuracy Absolute DC Offset Output Voltage Load Resistance Digital Filter Performance Pass band

CONDITIONS

MIN

TYP

MAX 200

500 -60dBFS 0dBFS -3dBFS

112 0.002

0.006 0.005

100

VO RL

Stop band Group Delay